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The simplest form of the VHDL handler could use the keyboard clock signal as the system clock and then monitor the data coming from the keyboard. This is shown here:
1 library ieee;
2 use ieee.std_logic_1164.all; 34 entity pskeyboard is
5 port ( 6 clock : in std_logic;
7 data : in std_logic
8 );
9 end entity pskeyboard;
10
11 architecture basic of pskeyboard is
12 signal d : std_logic_vector (23 downto 0);
13 signal byte1 : std_logic_vector (7 downto 0);
14 signal byte2 : std_logic_vector (7 downto 0);
15 signal byte3 : std_logic_vector (7 downto 0);
16 signal index : integer := 23;
17 begin
18 process(clock) is
19 begin
20 if falling_edge(clock) then
21 d(index) <= data;
22 if index>0 then
23 index <= index−1;
24 else
25 byte1 <= d(23 downto 16);
26 byte2 <= d(15 downto 8);
27 byte3 <= d(7 downto 0);
28 index<=23;
29 end if;
30 end if;
31 end process;
32 end architecture basic;
This VHDL is very simple. On each falling edge of the clock the current value of the data is read into the next element of the data array (d) and when the complete 24-bits packet has been read in (and index has counted down to zero) then the three bytes are transcribed from the packet.
Modifified PS/2 Keyboard Handler in VHDL
The trouble with the previous keyboard handler is that, although syntactically correct, there could be noise on the keyboard clock and data signals leading to an incorrect clocking of the data and so another approach would be to have a much higher frequency signal clock and to monitor the PS/2 clock as if it were a signal. An extra check would be to filter the PS/2 clock so that only if there were a certain number of the same values would the clock be considered to have changed.
1 library ieee;
2 use ieee.std_logic_1164.all; 34 entity pskeyboard is
5 port ( 6 clk : in std_logic;
7 ps2_clock : in std_logic;
8 data : in std_logic
9 );
10 end entity pskeyboard;
11
12 architecture basic of pskeyboard is
13 signal clk_internal : std_logic := 0 ;
14 signal d : std_logic_vector (23 downto 0);
15 signal byte1 : std_logic_vector (7 downto 0);
16 signal byte2 : std_logic_vector (7 downto 0);
17 signal byte3 : std_logic_vector (7 downto 0);
18 signal index : integer := 23;
19 begin
20 process(clock) is
21 high : integer := 0;
22 low : integer := 0;
23 begin
24 if rising_edge(clock) then
25 if (ps2_clock = 1 ) then
26 if high=8 then
27 clk_internal <= 1 ;
28 high <= 0;
29 low <= 0
30 else
31 high <= high +1;
32 end if;
33 else
34 if low=8 then
35 clk_internal <= 0 ;
36 low <= 0;
37 high <= 0;
38 else
39 low <= low +1;
40 end if;
41 end if;
42 end if;
43 end process;
44 process(clk_internal) is
45 begin
46 if falling_edge(clk_internal) then
47 d(index) <= data;
48 if index>0 then
49 index <= index−1;
50 else
51 byte1 <= d(23 downto 16);
52 byte2 <= d(15 downto 8);
53 byte3 <= d(7 downto 0);
54 index<=23;
55 end if;
56 end if;
57 end process;
58 end architecture basic;
In this case the modified keyboard handler waits for eight consecutive highs or lows on the clock signal at the higher internal clock rate of the FPGA and then it will set the internal clock high or low, respectively. Then the same keyboard handler routine takes over to manage the data input, this time using the internally generated clock.
The simplest form of the Verilog handler could use the keyboard clock signal as the system clock and then monitor the data coming from the keyboard; this is shown here:
1 module pskeyboard (
2 clk, / clock input
3 data / data input
4 );
56 input clk;
7 input data;
89 wire clk;
10 wire data;
11
12 reg [4:0] index = 5’b10111;
13 reg [23:0] d;
14 reg [7:0] byte1;
15 reg [7:0] byte2;
16 reg [7:0] byte3;
17
18 always @ (negedge clk)
19 begin : count
20 d[index] <= data;
21 if (index > 0) begin
22 index <= index − 1;
23 end
24 else begin
25 index <= 23;
26 byte1 <= d[23:16];
27 byte2 <= d[15:8];
28 byte3 <= d[7:0]
29 end
30 end
31
32 endmodule
This Verilog is very simple: On each falling edge of the clock the current value of the data is read into the next element of the data array (d) and when the complete 24-bits packet has been read in (and index has counted down to zero) then the three bytes are transcribed from the packet.
A modified handler could also be implemented in Verilog, either using the same approach as described for the VHDL model, but also the approach could be taken to simply divide down the clock from a higher frequency reference.
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