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The simplest form of the VHDL handler could use the mouse clock signal as the system clock and then monitor the data coming from the mouse. This is shown here:
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 entity psmouse is
5 port (
6 clock : in std_logic;
7 data : in std_logic
8 );
9 end entity psmouse;
10
11 architecture basic of psmouse is
12 signal d : std_logic_vector (23 downto 0);
13 signal byte1 : std_logic_vector (7 downto 0);
14 signal byte2 : std_logic_vector (7 downto 0);
15 signal byte3 : std_logic_vector (7 downto 0);
16 signal index : integer :$=$ 23;
17 begin
18 process(clock) is
19 begin
20 if falling_edge(clock) then
21 d(index) <= data;
22 if index>0 then
23 index <= index−1;
24 else
25 byte1 <= d(23 downto 16);
26 byte2 <= d(15 downto 8);
27 byte3 <= d(7 downto 0);
28 index<=23;
29 end if;
30 end if;
31 end process;
32 end architecture basic;
This VHDL is very simple: on each falling edge of the clock the current value of the data is read into the next element of the data array (d) and when the complete 24-bits packet has been read in (and index has counted down to zero) then the three bytes are transcribed from the packet.
Manufacturer:Xilinx
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Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
Product Categories: Dispositif de protection de circuit
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
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