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There are two approaches to minimizing the logic in a design, one that maintains the hierarchy and the other that flattens it. Often a synthesis tool will allow the user to choose which option is required. Clearly the advantage of flattening a design is that the logic can be considered as a whole, whereas if the logic hierarchy is maintained, then there may be structural aspects of the design that will be of benefit to the behavior of the circuit as a whole.
The basic approach of the logic minimization is to reduce the logic equation set to a two level form (otherwise known as sum-of-products). The most common approach for simple designs is to use a Karnaugh map to show the input and output variables graphically and then produce an output expression that can provide the same outputs but using a smaller amount of logic than the original Boolean expressions.
For example, consider the basic 4 input Karnaugh map shown in Figure 16.1. When a logic expression is described using a logic equation, we can select all valid outputs by circling all the required output 1s and this defines the basic logic behavior. The basic technique is to make the circles as large as possible to encompass as many output 1s with as few input variables as possible. For example, if a basic logic equation was defined as
Figure 16.1
Basic 4 input Karnaugh map
Figure 16.2
Specifific Karnaugh map example.
then the resulting Karnaugh map would be as shown in Figures 16.2 and 16.3.
Currently, with this basic implementation this would require three, 3 input AND gates, a 3 input OR gate and several inverters. We can see from the Karnaugh map, however, that if we define only two of those logic functions, then there is redundancy in the original definition, and we can reduce this to the same output for two logic combinations of the input.
We could therefore define this model using the simplified expression given in Equation (16.2)
This has clearly reduced the size of the logic by one 3 input AND gate and the OR gate has reduced to a 2 input gate.
Figure 16.3
Karnaugh Map functions.
Figure 16.4
Naive dataflflow diagram for addition.
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