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As has been discussed previously, flash memory is essentially a form of EEPROM (Electrically Erasable and Programmable Read Only Memory). This is slightly different from a standard RAM where the address is given to the memory and depending on the R/W signals, the data is read or written, respectively. A typical set of interface pins for a flash memory consists of the following elements:
Figure 11.5
Basic Verilog SRAM Simulation.
In addition to these control signals there is of course an address bus and a data bus. To implement this we can use a similar entity to that for a standard RAM block in VHDL:
1 entity flash is
2 generic ( 3 a : natural := 10;
4 d : natural := 8
5 );
6 port ( 7 clk : in std_logic;
8 addr : in std_logic_vector(a−1 downto 0);
9 data : inout std_logic_vector (d−1 downto 0);
10 cle : in std_logic;
11 ale : in std_logic;
12 ce : in std_logic;
13 re : in std_logic;
14 we : in std_logic;
15 wp : in std_logic;
16 busy : out std_logic;
17 );
18 end entity flash;
In most cases we won’t need to model the flash memory itself, but rather we need to interface to it, so the entity for a flash interface controller could be as follows:
1 entity flashif is
2 port ( 3 clk : in std_logic;
4 read : in std_logic;
5 en : in std_logic;
6 cle : out std_logic;
7 ale : out std_logic;
8 ce : out std_logic;
9 re : out std_logic;
10 we : out std_logic;
11 wp : out std_logic;
12 busy : in std_logic;
13 );
14 end entity flashif;
A typical architecture for this device could be as follows:
1 architecture basic of flashif is
2 begin
3 process (clk) is
4 if busy = 1 then
5 if rising_edge(clk) then
6 ce <= en;
7 ale <= 1 ;
8 cle <= 1 ;
9 if read = 0 then
10 we <= 1 ;
11 re <= 1 ;
12 else
13 we <= 0 ;
14 re <= 0 ;
15 end if;
16 if prog = 0 then
17 wp <= 0 ;
18 else
19 wp <= 1 ;
20 end if;
21 end if;
22 end if;
23 end process;
24 end architecture basic;
This is a basic outline for a flash controller and this will obviously change from device to device.
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