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Read only memory (ROM) is essentially a set of predefined data values in a storage register. The memory has two definitions: first, the number of storage areas and second, the number of bits. For example, if the memory has 16 storage areas and 8 bits each, the memory is defined as a 16 × 8 ROM. The basic ROM has one input, the definition of the address to be accessed, and one output, which is a logic vector which is where the data will be put. Consider as an example the entity for a simple behavioral ROM model in VHDL:
1 entity ROM16x8 is
2 port ( 3 address : in integer range 0 TO 15;
4 dout : out std_logic_vector (7 downto 0)
5 );
6 end entity ROM16x8;}
As can be seen, the address has been defined as an integer, but the range has been restricted to the range of the ROM. The architecture of the ROM is defined as a fixed array of elements that can be accessed directly. Therefore, an example ROM with a set of example data elements could be defined as follows:
1 architecture example of rom16x8 is
2 type romdata is array (0 to 15)
3 of std_logic_vector( 7 downto 0);
4 constant romvals : romdata := (
5 ”00000000”,
6 ”01010011”,
7 ”01110010”,
8 ”01101100”,
9 ”01110101”,
10 ”11010111”,
11 ”11011111”,
12 ”00111110”,
13 ”11101100”,
14 ”10000110”,
15 ”11111001”,
16 ”00111001”,
17 ”01010101”,
18 ”11110111”,
19 ”10111111”,
20 ”11101101”);
21 begin
22 data <= romvals(address);
23 end architecture example;
If we wish to use this in an example, we first need to declare the ROM in a VHDL testbench and then specify the address using an integer signal. A sample testbench is given here:
1 library ieee;
2 use ieee.std_logic_1164.all; 34 entity ROM16x8_TB is
5 end entity ROM16x8_TB;
67 architecture TB of ROM16x8_TB is
8 signal address : integer := 0;
9 signal data : std_logic_vector ( 7 downto 0 );
10 begin
11 ROM16x8: entity work.ROM16x8(example)
12 port map ( address, data );
13 end architecture TB;
Notice that the IEEE library, std_logic_1164, is required for the std_logic_vector type and the value of the data will depend on the address chosen.
We can implement a very similar type of fixed ROM using a case statement in Verilog and the listing for the equivalent 16 × 8 ROM is provided as follows:
1 module rom16x8 (
2 address , / Address input
3 data , / Data output
4 );
5 input [3:0] address;
6 output [7:0] data;
78 reg [7:0] data ;
9
10 always @ (address)
11 begin
12 case (address)
13 0 : data = 8’b00000000;
14 1 : data = 8’b01010011;
15 2 : data = 8’b01110010;
16 3 : data = 8’b01101100;
17 4 : data = 8’b01110101;
18 5 : data = 8’b11010111;
19 6 : data = 8’b11011111;
20 7 : data = 8’b00111110;
21 8 : data = 8’b11101100;
22 9 : data = 8’b10000110;
23 10 : data = 8’b11111001;
24 11 : data = 8’b00111001;
25 12 : data = 8’b01010101;
26 13 : data = 8’b11110111;
27 14 : data = 8’b10111111;
28 15 : data = 8’b11101101;
29 endcase
30 end
31
32 endmodule
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