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The VHDL for a simple LCD decoder uses a simple VHDL construct setting the output depending on a specific condition. If a signal is assigned a value when a condition is satisfied, then a single assignment can be made using the following basic pseudocode:
Figure 27.1 7 segment LCD display.
1 output <= value when condition;
This can be extended with else statements to cover a set of different conditions, thus:
1 output <= value1 when condition1 else
2 value2 when condition2 else
3 .
4 valuen when condition;
Finally, if there is a “catch all” default condition, then the final assignment would be added as follows:
1 output <= value1 when condition1 else
2 value2 when condition2 else
3 .
4 valuen when conditionn else
5 valuedefault;
This could also be implemented as a dedicated VHDL function which returned the correct combination of bits. Using this approach, the LCD decoder can be simply implemented using the following VHDL:
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity hexdecoder is
6 port (
7 charin : in std_logic_vector (3 downto 0);
8 hexout : out std_logic_vector(6 downto 0)
9 );
10 end;
11
12 architecture simple of hexdecoder is
13 begin
14 hexout <= "1000000" when charin = "0000" else
15 "1111001" when charin = "0001" else
16 "0100100" when charin = "0010" else
17 "0110000" when charin = "0011" else
18 "0011001" when charin = "0100" else
19 "0010010" when charin = "0101" else
20 "0000010" when charin = "0110" else
21 "1111000" when charin = "0111" else
22 "0000000" when charin = "1000" else
23 "0011000" when charin = "1001" else
24 "0001000" when charin = "1010" else
25 "0000011" when charin = "1011" else
26 "1000110" when charin = "1100" else
27 "0100001" when charin = "1101" else
28 "0000110" when charin = "1110" else
29 "0001110" when charin = "1111" else
30 "0110110";
31 end;
The test bench for this decoder could be a simple look-up table of values, but in fact we could combine the clock and reset test bench from the counter example, and include a simple counter in the test bench to generate the signals input to the decoder as follows:
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity test1 is
6 port (
7 rst : in std_logic;
8 clk : in std_logic;
9 hexout : out std_logic_vector(6 downto 0)
10 );
11 end test1;
12
13 architecture stimulus of test1 is
14 signal charin : std_logic_vector(3 downto 0);
15
16 component hexdecoder
17 port(
18 charin : in std_logic_vector(3 downto 0);
19 hexout : out std_logic_vector(6 downto 0)
20 );
21 end component;
22 for all : hexdecoder use entity work.hexdecoder ;
23
24 begin
25
26 CUT: hexdecoder port map(charin => charin, hexout => hexout);
27
28 process(clk, rst)
29 variable count : unsigned(26 downto 0);
30 variable charcount : unsigned(3 downto 0);
31 begin
32 if rst = ’0’ then
33 count := (others => ’0’);
34 charcount := (others => ’0’);
35 elsif rising_edge(clk) then
36 if count = 50000000 then
37 count := (others => ’0’);
38 charcount := charcount + 1;
39 else
40 count := count + 1;
41 end if;
42 end if;
43 charin <= std_logic_vector(charcount);
44 end process;
45 end;
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