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We can use the same simple approach in Verilog as we have just seen in VHDL, where the use of the basic unsigned types and a multiplication can be defined in the code directly, and then the synthesis software will take care of the translation into a physical multiplier.
In the multiplier model in Verilog, we can use a simple assignment as shown in the code snippet following, where the always statement is used to check for changes in a or b before assigning the output q to the product. This requires the definition of the output as a register (but we could also use the approach of defining the output as a wire and using the assign statement instead).
1 always @ (a or b)
2 begin
3 q <= a ∗ b;
4 end
The complete multiplier model is given in the following listing:
1 module signmult (
2 q, / Multiplication Output
3 a, / Number a
4 b / Number b
5
6 );
7
8 input [3:0] a; / 4 bit input
9 input [3:0] b; / 4 bit input
10 output [7:0] q; / 8 bit output
11 reg [7:0] q;
12
13 always @ (a or b)
14 begin
15 q <= a ∗ b;
16 end
17
18 endmodule
Figure 26.2 Unsigned multiplication of Verilog.
In order to test the model we can create a very simple test bench that defines the two variables (a and b), and after initializing them to zero, sets them to 6 and 4, respectively. The resulting simulation results are shown in Figure 26.2, which shows the output start at 0 (0 × 0), remain at 0 (0 × 4) and then finally change to 24 (6 × 4).
1 module signmult_tb();
2
3 reg [3:0] a,b;
4 wire [7:0] q;
5
6 signmult m1(q,a,b);
7
8 initial
9 begin
10
11 a = 4’b0000;
12 b = 4’b0000;
13 # 10 a = 4’b0110;
14 # 10 b = 4’b0100;
15
16 $display("a=%d b=%d q=%d\n", a, b, q);
17 end
18
19 endmodule
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