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The NRZ encoding scheme is actually not a coding scheme at all. It simply states that a 0 is transmitted as a 0 and a 1 is transmitted as a 1. It is only worth mentioning because a designer may see the term NRZ and assume that a specific encoder or decoder was required, whereas in fact this is not the case. It is also worth noting that there are some significant disadvantages in using this simple approach. The first disadvantage, especially when compared to the Manchester coding scheme, is that long sequences of 0s or 1s give effectively DC values when transmitted, which are susceptible to problems of noise and also make clock recovery very difficult. The other issue is that of bandwidth. Again if we compare the coding scheme to that of the Manchester example, it is obvious that the Manchester scheme requires quite a narrow bandwidth (relatively) to transmit the data, whereas the NRZ scheme may require anything from DC up to half the data rate (Nyquist frequency) and anything in between. This makes line design and filter design very much more problematic.
NRZI Coding and Decoding in VHDL
It is a simple matter to create a basic model for a NRZI encoder using the following VHDL model:
1 entity nrzi_encoder is
2 port ( 3 clk : in std_logic;
4 d : in std_logic;
5 q : out std_logic
6 );
7 end entity nrzi_encoder;
89 architecture basic of nrzi_encoder is
10 signal qint : std_logic := 0 ;
11 begin
12 p1 : process (clk)
13 begin
14 if (d = 1 ) then
15 if ( qint = 0 ) then
16 qint <= 1 ;
17 else
18 qint <= 0 ;
19 end if;
20 end if;
21 end process p1;
22 q <= qint;
23 end architecture basic;
Notice that this model is synchronous, but if we wished to make it asynchronous, the only changes would be to remove the clk port and change the process sensitivity list from clk to d. We can apply the same logic to the output, to obtain the decoded data stream, using the VHDL as follows. Again we are using a synchronous approach:
1 entity nrzi_decoder is
2 port ( 3 clk : in std_logic;
4 d : in std_logic;
5 q : out std_logic
6 );
7 end entity nrzi_decoder;
89 architecture basic of nrzi_decoder is
10 signal lastd : std_logic := 0 ;
11 begin
12 p1 : process (clk)
13 begin
14 if rising_edge(clk) then
15 if (d = lastd) then
16 q <= 0 ;
17 else
18 q <= 1 ;
19 end if;
20 lastd <= d;
21 end if;
22 end process p1;
23 end architecture basic;
The NRZI decoder is extremely simple, in that the only thing we need to check is whether the data stream has changed since the last clock edge. If the data has changed since the last clock, then we know that the data is a 1, but if the data is unchanged, then we know that it is a 0. Clearly we could use an asynchronous approach, but this would rely on the data checking algorithm downstream being synchronized correctly.
NRZI Coding and Decoding in Verilog
It is a simple matter to create a basic model for a NRZI encoder using the following Verilog model:
1 module nrzi_encoder (
2 clk, / CLock Input
3 d, / Data Input
4 q / Data Output
5 );
67 input clk;
8 input d;
9 output q;
10
11 reg q;
12
13 reg qint;
14
15 always_init
16 begin
17 qint <= 0;
18 end
19
20 always @ (clk)
21 begin
22 if d=1
23 if qint = 0
24 qint <= 1
25 else
26 qint <= 0
27 end
28
29 end
30 q <= qint;
31 end
32 endmodule
Notice that this model is synchronous, but if we wished to make it asynchronous, the only changes would be to remove the clk port and change the process sensitivity list from clk to d. We can apply the same logic to the output, to obtain the decoded data stream, using the Verilog that follows. Again we are using a synchronous approach:
1 module nrzi_encoder (
2 clk, / CLock Input
3 d, / Data Input
4 q / Data Output
5 );
67 input clk;
8 input d;
9 output q;
10
11 reg q;
12
13 always @ (clk)
14 begin
15 if clk=1 begin
16 if d=lastd
17 q <= 0;
18 else
19 q <= 1;
20 end
21 end
22 end
23 endmodule
The NRZI decoder is extremely simple, in that the only thing we need to check is whether the data stream has changed since the last clock edge. If the data has changed since the last clock, then we know that the data is a 1, but if the data is unchanged, then we know that it is a 0. Clearly we could use an asynchronous approach, but this would rely on the data checking algorithm downstream being synchronized correctly.
Manufacturer:Xilinx
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories: Disjoncteur
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
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