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As we have seen in the previous example, there is a method of implementing multiplication operations using a “first principles” approach and it is incredibly hungry in terms of both resources and time (taking n shifts to complete a multiplication would lead to a really slow device).
There is, however, an alternative approach with many modern FPGAs that include multiplier blocks as part of the design. These are custom multiplication blocks already in place on the FPGA and this allows the specific multiply function to be implemented directly in the VHDL.
We can therefore convert the std_logic_vector signals into signed signals and then apply the product equation directly using the following VHDL (remember a and b are the two inputs, both of type std_logic_vector, and product is the output, also of type std_logic_vector).
1 Product <= std_logic_vector( signed(a) ∗ signed(b) );
Clearly this is much more efficient VHDL than the previous model, but also remember that it is necessary to declare the IEEE numeric standard library:
1 Use ieee.numeric_std.all;
This allows the use of the signed variable types. The complete model using this approach is much more compact and is shown below:
1 library ieee;
2 use IEEE.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity mult_sign is
6 generic(top : natural := 15);
7 port (
8 clk : in std_logic;
9 nrst : in std_logic;
10 a : in std_logic_vector (top downto 0);
11 b : in std_logic_vector (top downto 0);
12 product : out std_logic_vector (2∗top+1 downto 0)
13 );
14 end entity mult_sign;
15
16 architecture behavior of mult_sign is
17 begin
18 p1 : process (a,b)
19 begin
20 product <= std_logic_vector(signed(a) ∗ signed(b));
21 end process p1;
22 end architecture behavior;
The resulting synthesis output is much more compact. Clearly the number of IO blocks (IOBs) will remain the same, but the usage internally on the FPGA will be much reduced:
Number of ports : 66
Number of nets : 128
Number of instances : 65
Number of references to this view : 0
Total accumulated area :
Number of Block Multipliers : 1
Number of gates : 0
Number of accumulated instances : 65
Number of global buffers used: 0
***********************************************
Device Utilization for 2VP2fg256
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 66 140 47.14%
Global Buffers 0 16 0.00%
Function Generators 0 2816 0.00%
CLB Slices 0 1408 0.00%
Dffs or Latches 0 3236 0.00%
Block RAMs 0 12 0.00%
Block Multipliers 1 12 8.33%
Clearly, for this device, there are 12 multipliers available, and we have used only one, so the utilization of the remainder of the device is zero. This does lead to the ability to implement certain lower order filters very effectively using devices such as these.
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