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If we start with a simple unsigned multiplier, then this can be implemented very simply using VHDL. The important aspect to consider with this multiplier is how many bits will be on the inputs and how many on the output. If the number of bits are the same across all three, then we need to consider the possibility of overflow and how this can be handled by the multiplier.
In this basic model, we will define the output number of bits as being the sum of the two input word lengths, and deal with overflow externally to the multiplier.
If we use the basic accumulator and addition function of the simple binary addition method described previously, we can implement a basic VHDL multiplier as shown below:
1 library ieee;
2 use IEEE.std_logic_1164.all;
3
4 entity mult_beh is
5 generic(top : natural := 15);
6 port (
7 clk : in std_logic;
8 nrst : in std_logic;
9 a : in std_logic_vector (top downto 0);
10 b : in std_logic_vector (top downto 0);
11 product : out std_logic_vector (2∗top+1 downto 0)
12 );
13 end entity mult_beh;
14
15 architecture behavior of mult_beh is
16 component add_beh
17 generic (
18 top : integer := 7
19 );
20 port (
21 signal a : in std_logic_vector(top downto 0);
22 signal b : in std_logic_vector(top downto 0);
23 signal cin : in std_logic;
24 signal cout : out std_logic;
25 signal sum : out std_logic_vector(top downto 0)
26 );
27 end component;
28 for all : add_beh use entity work.add_beh;
29
30 signal cin : std_logic := ’0’;
31 signal cout : std_logic := ’0’;
32 signal acc : std_logic_vector(2∗top+1 downto 0);
33 signal sum : std_logic_vector(2∗top+1 downto 0);
34 signal mand : std_logic_vector(2∗top+1 downto 0);
35 signal index : integer := 0;
36 signal finished : std_logic := ’0’;
37 begin
38
39 DUT :add_beh generic map (2∗top+1) port map (acc,mand,cin,cout,sum);
40
41 p1 : process (clk, nrst)
42 variable mandvar : std_logic_vector(2∗top+1 downto 0);
43 begin
44 if (nrst = ’0’) then
45 acc <= (others => ’0’);
46 index <= 0;
47 finished <= ’0’;
48 else
49 if clk’event then
50 if clk = ’1’ then
51 if index <= top then
52 index <= index + 1;
53 mandvar := (others => ’0’);
54 if b(index) = ’1’ then
55 for i in 0 to top loop
56 mandvar(i+index) := a(i);
57 end loop;
58 end if;
59 end if;
60 mand <= mandvar;
61 acc <= sum;
62 else
63 if index > top−1 then
64 finished <= ’1’;
65 end if;
66 end if;
67 end if;
68 end process p1;
69 p2 : process ( finished)
70 begin
71 if rising_edge(finished) then
72 product <= sum;
73 end if;
74 end process p2;
75 end architecture behavior;
This model is perhaps more complex than it really needs to be, but it does have some nice features from a learning point of view.
Firstly, rather than a “super efficient” shifting model which is difficult to read, the shift and add function in process p1 is laid out in detail so each stage of the multiplication can be followed through. Also, notice the use of the signal finished which is used to show when the calculation is completed. This is useful when designing a controller to show that the calculation has been completed.
Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories: Industrial components
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