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The Verilog code for the synchronous Manchester encoder is shown here:
1 module manchester (
2 clk, / clock input
3 d, / data input
4 q / encoded output
5 );
67 input clk;
8 input d;
9
10 output q;
11 reg q;
12 reg lastd;
13
14 always_init begin
15 lastd <= 0;
16 end
17
18 always @ (clk)
19 begin
20 if clk=’1’ begin
21 if d=1 then
22 begin
23 q <= 1;
24 lastd <= 0;
25 end
26 else
27 begin
28 q <= 0;
29 lastd <= 1;
30 end
31 end
32 else
33 begin
34 if lastd = 0 then
35 q <= 0;
36 else
37 q = 1;
38 end
39 end
40 endmodule
The XOR implementation of the Manchester encoder is much simpler and this listing is shown as follows:
1 module manchester_xor (
2 clk, / clock input
3 d, / data input
4 q / encoded output
5 );
67 input clk;
8 input d;
9
10 output q;
11 reg q;
12
13 q <= clk xor d;
14
15 endmodule
Decoding the Manchester data stream is also a choice between asynchronous and synchronous approaches. We can use a local clk and detect the values of the input to evaluate whether the values on the rising and falling edges are 0 or 1, respectively, and ascertain the values of the data as a result, but clearly this is dependent on the transmitter and receiver clocks being synchronized to a reasonable degree. Such a simple decoder could look like this:
1 entity manchester_decoder is
2 port (
3 clk : in std_logic;
4 d : in std_logic;
5 q : out std_logic
6 );
7 end entity manchester_decoder;
89 architecture basic of manchester_decoder is
10 signal lastd : std_logic := 0 ;
11 begin
12 p1 : process (clk)
13 begin
14 if clk’event and clk=’1’ then
15 lastd <= d;
16 else
17 if (lastd = 0 ) and (d = 1 ) then
18 q <= 1 ;
19 elsif (lastd = 1 ) and (d= 0 ) then
20 q <= 0 ;
21 else
22 q <= x ;
23 end if;
24 end if;
25 end process p1;
26 end architecture basic;
In this Verilog model, the clock is at the same rate as the transmitter clock, and the data should be sent in packets to ensure that the data is not sent in too large blocks such that the clock can get out of sync, and also that the data can be checked for integrity to correct for mistakes or the clock on the receiver being out of phase.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Disjoncteur
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Disjoncteur
Lifecycle:Obsolete -
RoHS:
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