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The VHDL code for the synchronous Manchester encoder is shown here:
1 library ieee;
2 use ieee.std_logic_1664.all; 34 entity manchester_encoder is
5 port ( 6 clk : in std_logic;
7 d : in std_logic;
8 q : out std_logic
9 );
10 end entity manchester_encoder;
11
12 architecture basic of manchester_encoder is
13 signal lastd : std_logic := 0 ;
14 begin
15 p1: process ( clk )
16 begin
17 if clk’event and clk=’1’ then
18 if (d=0 ) then
19 q <= 1 ;
20 lastd <= 0 ;
21 elsif (d=1) then
22 q <= 0 ;
23 lastd <= 1 ;
24 else
25 q <= x ;
26 lastd <= x ;
27 end if;
28 else
29 if ( lastd = 0 ) then
30 q <= 0 ;
31 elsif ( lastd = 1 ) then
32 q <= 1 ;
33 else
34 q <= x ;
35 end if
36 end if;
37 end process p1;
38 end architecture basic;
The XOR implementation of the Manchester encoder is much simpler and this listing is shown as follows:
1 library ieee;
2 use ieee.std_logic_1664.all; 34 entity manchester_encoder is
5 port ( 6 clk : in std_logic;
7 d : in std_logic;
8 q : out std_logic
9 );
10 end entity manchester_encoder;
11
12 architecture basic of manchester_encoder is
13 begin
14 q <= d xor clk;
15 end architecture basic;
Decoding the Manchester data stream is also a choice between asynchronous and synchronous approaches. We can use a local clk and detect the values of the input to evaluate whether the values on the rising and falling edges are 0 or 1, respectively, and ascertain the values of the data as a result, but clearly this is dependent on the transmitter and receiver clocks being synchronized to a reasonable degree. Such a simple decoder could look like this:
1 entity manchester_decoder is
2 port ( 3 clk : in std_logic;
4 d : in std_logic;
5 q : out std_logic
6 );
7 end entity manchester_decoder;
89 architecture basic of manchester_decoder is
10 signal lastd : std_logic := 0 ;
11 begin
12 p1 : process (clk)
13 begin
14 if clk’event and clk=’1’ then
15 lastd <= d;
16 else
17 if (lastd = 0 ) and (d = 1 ) then
18 q <= 1 ;
19 elsif (lastd = 1 ) and (d= 0 ) then
20 q <= 0 ;
21 else
22 q <= x ;
23 end if;
24 end if;
25 end process p1;
26 end architecture basic;
In this VHDL model, the clock is at the same rate as the transmitter clock, and the data should be sent in packets to ensure that the data is not sent in blocks that are too large, such that the clock can get out of sync, and also that the data can be checked for integrity to correct for mistakes or the clock on the receiver being out of phase.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: CPLD/FPGA
Lifecycle:Obsolete -
RoHS: -
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