A VGA Interface in Verilog

A VGA Interface in Verilog

Verilog Top Level Module for VGA Handling

The first stage in defining the Verilog for the VGA driver is to create a module that has the global clock and reset, the VGA output pins, and a memory interface. The outline Verilog module is therefore given as follows:1 module vga (

2 clk, / clock input

3 nrst, / reset

4 hsync, / hsync

5 vsync, / vsync

6 red, / red output

7 green, / green output

8 blue, / blue output

9 address, / address output

10 data, / data

11 ram_en, / RAM enable

12 ram_oe, / RAM Output Enable

13 ram_wr / RAM write signal

14 );

The module contains a number of processes, with internal signals that manage the transfer of pixel data from memory to the screen. As before, the data comes back from the memory in 8-bit blocks and we require 3 × 2 bits for each pixel and so when the data is returned, each memory byte will contain the data for a single pixel. In this example, as we are using a 640 × 480 pixel image, this will therefore require a memory that is 307,200 bytes in size as a minimum. To put this in perspective, this means that using a raw memory approach we can put three frames per megabyte. In practice, of course, we would use a form of image compression (such as JPEG for photographic images), but this is beyond the scope of this book.

We can therefore use a simple process to obtain the current pixel of data from memory as follows:

1 always @ (posedge pclk)

2 begin

3 if (nrst = 0) begin

4 pixelcount <= 0;

5 current_address <= 0;

6 else

7 current_address <= current_address + 1;

8 address <= current_address;

9 pixel_data <= data;

11 end

12 end

This process returns the current value of the pixel data into a signal called pixel_data which is declared at the module level:

1 reg [7:0] pixel_data;

This has the red, green, and blue data defined in the lowest 6 bits of the 8-bit data word with the indexes, respectively, of 0-1, 2-3, and 4-5.

Horizontal Sync

The next key process is the timing of the horizontal and vertical sync pulses, and the blanking intervals. The line timing for VGA is 31,770 ns per line with a window for displaying the data of 25,170 ns. If the FPGA is running at 100 MHz (period of 10 ns) then this means that each line requires 3177 clock cycles with 2517 for each line of pixel data, with 660 pulses in total for blanking (330 at either side). This also means that for a 640 pixel wide line, 39.3 ns are required for each pixel. We could round this up to 4 clock cycles per pixel. As you may have noticed, for the pixel retrieval we have a new internal clock signal called pclk, and we can create a process that generates the appropriate pixel clock (pclk) with this timing in place.

With this slightly elongated window, the blanking pulses must therefore reduce to 617 clock cycles and this means 308 before and 309 after the display window.

The horizontal sync pulse, on the other hand, takes place between 26,110 ns and 29,880 ns of the overall interval. This is 189 clock pulses less than the overall line time, and so the horizontal sync pulse goes low after 94 clock cycles and then at the end must return high 95 clock cycles prior to the end of the line. The difference between the outside and inside timings for the horizontal sync pulse is 377 clock cycles and so the sync pulse must return high 94 + 188 clock cycles and then return low 95 + 189 prior to the end of the window.

Thus, the horizontal sync has the same behavior as described previously in this chapter and this can be implemented using a process with a simple counter:

1 always @ (posedge clk)

2 begin

3 if (nrst = 0) begin

4 hcount <= 0;

5 hsync <= 1;

6 end

7 else

8 if (hcount > 2611) and (hcount<2988) begin

9 hsync <= 0;

10 else

11 hsync <= 1;

12 end if

13 if (hcount < 3177) begin

14 hcount <= hcount + 1;

15 else

16 hcount <= 0;

17 end if

18 end if

19 end

Vertical Sync

The horizontal sync process manages the individual pixels in a line, and the vertical sync does the same for the lines as a whole to create the image. The period of a frame (containing all the lines) is defined as 16,784,000 ns. Within this timescale, the lines of the image are displayed (within 15,250,000 ns), then the vertical blanking interval is defined (up to the whole frame period of 16,784,000 ns) and finally the vertical sync pulse is defined as 1 until 15,700,000 ns at which time it goes to zero, returning to 1 at 15,764,000 ns.

Clearly it would not be sensible to define a clock of 10 ns for these calculations, so the largest common divisor is a clock of 2 s, so we can divide down the system clock by 2000 to get a vertical sync clock of 2 s to simplify and make the design as compact as possible.

1 always @ (posedge clk) begin

2 if (nrst = 0) begin

3 count <= 0;

4 vclk <= 0;

5 else

6 if (count = 1999) begin

7 count <= 0;

8 vclk <= not vclk;

9 else

10 count <= count + 1;

11 end if

12 end if

13 end

where the vertical sync clock (vclk) is defined as a std_logic signal in the architecture. This can then be used to control the vsync pulses in a second process that now waits for the vertical sync derived clock:

1 always @ (vclk) begin

2 if nrst = 0 begin

3 vcount <= 0;

4 else

5 if vcount>15700 and vcount <15764 begin

6 vsync <= 0;

7 else

8 vsync <= 1;

9 end if

10 if vcount > 16784 begin

11 vcount <= 0;

12 else

13 vcount <= vcount + 1;

14 end if

15 end if

16 end

Using this process, the vertical sync (frame synchronization) pulses are generated.

Horizontal and Vertical Blanking Pulses

In addition to the basic horizontal and vertical sync pulse counters, we have to define a horizontal blanking pulse, which sets the line data low after 25,170 ns (2517 clock cycles). This can be implemented as a simple counter in exactly the same way as the horizontal sync pulse and similarly for a vertical blanking pulse. The two processes to implement these are given in the following VHDL.

1 always @ (posedge clk) begin

23 if nrst = 0 begin

4 hcount <= 0;

5 hblank <= 1;

6 end

7 else

8 if hcount > 2517 and hcount<3177 begin

9 hblank <= 0;

10 else

11 hblank <= 1;

12 end if

13 if hcount < 3177 then

14 hcount <= hcount + 1;

15 else

16 hcount <= 0;

17 end if

18 end if

19 end

21 always @ (posedge vclk) begin

22 if nrst = 0 begin

23 vcount <= 0;

24 vblank<= 1 l

25 end

26 else

27 if vcount>15250 and vcount <16784 begin

28 vblank <= 0;

29 else

30 vblank <= 1;

31 end if

32 if vcount > 16784 begin

33 vblank <= 0;

34 else

35 vcount <= vcount + 1;

36 end if

37 end

38 end

Calculating the Correct Pixel Data

As we have seen previously, the data of each pixel is retrieved from a memory location and this is obtained using the pixel clock (pclk). The pixel clock is simply a divided (by 4) version of the system clock and at each rising edge of this pclk signal, the next pixel data is obtained from the memory data stored in the signal called data and translated into the red, green and blue line signals. This is handled using a similar process as was used for the VHDL.

This is the final step and completes the basic Verilog VGA handler.

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