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As stated previously, we can use these functions to incorporate standard std_logic ALU functions into the model. In this simple test case, we are using the standard n-bit adder created in Chapter 21 on ALUs to add two fixed point numbers together. How does this work? What we do is convert the two input fixed point numbers into std_logic_vectors, apply them to the adder block, then convert the output back to a fixed point number. We can convert both inputs and output into real numbers for observation on the screen. Note that although the representation of numbers is different, the values are the same. Also, this is a low-level approach that could be carried out using synthesis of the numeric_std equivalent types.
1 library ieee;
2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 45 use work.fp_pkg.all; 67 entity simple1 is
8 end entity simple1;
9
10 architecture tb of simple1 is
11 signal clk : std_logic := ’0’;
12 signal cin : std_logic := ’0’;
13 signal cout : std_logic;
14 signal testa : fp8_3 := "000000000000";
15 signal testa1 : fixsign ( 8 downto −3 );
16 signal testa2 : fixsign ( 8 downto −3 );
17 signal testb1 : fixsign ( 8 downto −3 );
18 signal testsum : fixsign ( 8 downto −3 );
19 signal as : signed ( 11 downto 0) := X"000";
20 signal a1std : std_logic_vector ( 11 downto 0) := X"800";
21 signal b1std : std_logic_vector ( 11 downto 0) := X"800";
22 signal sum : std_logic_vector ( 11 downto 0) ;
23 signal a1out : real;
24 signal b1out : real;
25 signal a2out : real;
26 signal sumout : real;
27 signal a1 : integer := 0;
28 signal bs : signed ( 11 downto 0) := X"8f0";
29
30 component add_beh
31 generic (
32 top : integer := 7
33 );
34 port (
35 signal a : in std_logic_vector(top downto 0);
36 signal b : in std_logic_vector(top downto 0);
37 signal cin : in std_logic;
38 signal cout : out std_logic;
39 signal sum : out std_logic_vector(top downto 0)
40 );
41 end component;
42 for all : add_beh use entity work.add_beh;
43
44
45 begin
46 clk <= not clk after 1 us;
47
48 DUT :add_beh generic map ( 11 ) port map ( a1std, b1std, cin, cout, sum);
49
50 p1 : process (clk)
51 begin
52 as <= as + 1;
53 testa1 <= signed2fp(as,8,−3);
54 testb1 <= signed2fp(bs,8,−3);
55 a1out <= fp2real(testa1,8,−3);
56 b1out <= fp2real(testb1,8,−3);
57 a1std <= fp2std_logic_vector(testa1,8,−3);
58
59 b1std <= fp2std_logic_vector(testb1,8,−3);
60 testa2 <= std_logic_vector2fp(a1std,8,−3);
61 testsum <= std_logic_vector2fp(sum,8,−3);
62 a2out <= fp2real(testa2,8,−3);
63 sumout <= fp2real(testsum,8,−3);
64 report "a1out : " & real’image(a1out);
65 report "a2out : " & real’image(b1out);
66 report "sumout : " & real’image(sumout);
67 end process p1;
68 end;
An important aspect to note in this model is the use of signals and a clock (clk). By making this model synchronous, we have ensured correct, predictable behavior, but on each clock cycle there are several delays built in. The final observed result on sumout (the real number output for display) will appear 2 clock cycles after the data is input to the model.
In this case we are using signed numbers as the original input (as) as these can be incremented easily and setting one number to a constant (bs). These inputs are converted to real numbers (a1out, b1out) that are displayed to the screen to show the results.
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