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The most important functions are the conversion between fixed point and std_logic_vector variables. If we can translate from one to the other, then we can use our standard logic functional blocks, where appropriate, on the fixed point data directly, rather than needing to come up with brand-new blocks every time. The easiest function is the mapping from fixed point to std_logic_vector and is simply a matter of starting from the LSB defined in the range of the fixed point number and then setting each bit on the output std_logic_vector in turn to the correct value. The VHDL for this is given as follows:
1 function fp2std_logic_vector (d:fixsign;top:integer;low:integer)
2 return std_logic_vector is
3 variable outval : std_logic_vector ( top−low downto 0 ) := (others => ’0’);
4 begin
5 for i in 0 to top−low loop
6 outval(i) := d(i+low);
7 end loop; 8 return outval;
9 end;
If we look at this function we can see that the arguments to the function are the fixed point number, and then the two integer values that denote the number of bits above and below the decimal point, respectively. For example, if our notation is 8.3, the function call in this case would be:
1 q <= fp2std_logic_vector(d,8,−3);
Notice the negative number denoting the bits below the decimal point. If you would prefer both numbers to be positive, they can simply be changed. One reason for using the negative form is that the numbers match the basic type definition and therefore make checking easy.
Similarly, we can convert from std_logic_vector back to fixed point using a very similar function in the opposite direction:
1 function std_logic_vector2fp
2 (d:std_logic_vector;top:integer;low:integer)
3 return fixsign is
4 variable outval : fixsign ( top downto low ) := (others => ’0’);
5 begin
6 for i in 0 to top−low loop
7 outval(i+low) := d(i);
8 end loop; 9 return outval;
10 end;
with the similar usage:
1 q <= std_logic_vector(d,8,−3);
Using these functions, the conversion between the std_logic_vector and fixed point arithmetic domains becomes straightforward. Also, these functions are easily synthesizable as they simply map bits and do not carry out any sophisticated functions other than that.
Fixed Point to Real Conversion
An extremely useful function is the ability to convert from fixed point to real numbers. Obviously this has no use for synthesis, but is ideal for adding checking and reports to test benches. As a result we only define a single function fp2real which takes a fixed point number and converts to a real number for display. Once we have the number, then the real’image function can be used to display the value. The VHDL for the conversion function is given here:
1 function fp2real (d:fixsign; top:integer; low:integer)
2 return real is
3 variable outreal : real := 0.0;
4 variable mult : real := 1.0;
5 variable max : real := 1.0;
6 variable debug : boolean := false;
7 begin
8 for i in 0 to top−1 loop
9 if d(i) = ’1’ then
10 outreal := outreal + mult;
11 if debug then
12 report " fp2real : " & integer’image(i);
13 end if;
14 end if;
15 mult := mult ∗ 2.0;
16 end loop;
17 if debug then
18 REPORT " fp2real middle : " & real’image(outreal);
19 end if;
20 max := mult;
21 mult := 0.5;
22 for i in −1 downto low loop
23 if d(i) = ’1’ then
24 outreal := outreal + mult;
25 if debug then
26 report " fp2real : " & integer’image(i);
27 end if;
28 end if;
29 mult := mult ∗ 0.5;
30 end loop;
31 if debug then
32 REPORT " fp2real : " & real’image(outreal);
33 end if;
34
35 if d(top) = ’1’ then
36 outreal := outreal − max;
37 end if;
38 if debug then
39 REPORT " fp2real FINAL VALUE : " & real’image(outreal);
40 end if;
41
42 return outreal;
43 end;
This function is a simple converter that handles the bits above and below the decimal point in turn. Also notice the internal Boolean debug variable that allows checking of each individual bit. This can be very useful when observing the passing of numbers across boundaries ensuring correct translation; this defaults to false (off). If we need to report a fixed point value, we can therefore use this function to report the values using simple VHDL such as this:
1 d : fp8_3;
2 dr : real;
3 dr <= fp2real(fp8_3,8,−3);
4 report "The value is : " & real’image(dr);
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Product Categories: FPGAs (Field Programmable Gate Array)
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