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The first task in defining a custom fixed point library is to specify a new type for the numbers. The closest similar types in standard VHDL that can be synthesized are unsigned and signed. These are defined in terms of a specific number of bits. In most cases we are interested in linking directly to std_logic systems, and so in this case we can effectively define a new type based on an array of std_logic bits. For the remainder of this chapter we will discuss signed arithmetic only, as this is the most potentially useful from a DSP and application point of view.
The basic VHDL type that defines our base type is to be called fixsign and is defined as an unrestricted array of std_logic:
1 type fixsign is array ( integer range <> ) of std_logic;
From this, we can define specific subtypes that have a defined range of fixed point. For example, we can define a type (this is often called a fractional integer type) that has 8 bits above the decimal point and 3 bits below (for example, 00000001.001) using the following declaration:
1 Subtype fp8_3 is fixsign ( 8 downto −3);
With this, we can declare signals of this new type and use them in fixed point VHDL models:
1 signal a1 : fp8_3;
2 a1 <= X0CA;
Clearly this is useful but limited, as this type needs to be able to be converted from one type to another easily and quickly. The simplest way to manage this process is to create a new package that contains not only the type declarations, but also the functions that are associated with this set of types. Therefore we can define a new package called fp_pkg that, as a minimum, contains these type declarations:
1 package fp_pkg is
2 type fixsign is array (integer range <>) of std_logic;
3 subtype fp8_3 is fixsign ( 8 downto −3);
4 end package; 56 package body fp_pkg is
7 −− The contents of the package go here
8 end package body;
We can now use this package in a VHDL model by compiling the package into the current work library and calling the package as we need it. We can also create a new library so that the package could be used more generally.
1 Use work.fp_pkg.all;
This will provide access to all the fixed point functions and types required. In this library, we have two types of functions. The first type is required for translating physical types (such as std_logic_vector) to our new types and vice versa. These are important as they will be synthesized and eventually end up on hardware. The second type are purely for debug purposes and displaying values. For example, it is useful to be able to convert fixed point data to real numbers and then use the real’image VHDL function to display the value. This could be extremely useful for debugging where a behavioral model would be able to represent real numbers, and so this could form a very helpful way to establish both the accuracy and validity of the “digital” equivalent system. A useful set of functions to facilitate this is therefore presented in this chapter. Again, these are exemplar functions, and readers are encouraged to develop these basic functions and produce their own for their own applications.
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