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The transition diagram can also be implemented in Verilog, again using two case statements (one for the state transitions and one for the outputs):
module fsm (
count, / Output Value
clk, / Clock
rst, / Reset
choice / Decision /Choice Value
);
output [1:0] count;
input clk;
input rst;
input choice;
reg [1:0] count;
reg [1:0] state; / state variable
parameter s0=0, s1=1, s2=2, s3=3;
always @(state)
begin
case (state)
s0:
count = 2’b00;
s1:
count = 2’b01;
s2:
count = 2’b10;
s3:
count = 2’b11;
default:
count = 2’b00;
endcase
end
always @(posedge clk or posedge rst)
begin
if (rst == 0)
state = s0;
else
case (state)
s0:
state = s1;
s1:
if (choice)
state = s3;
else
state = s2;
s2:
state = s0;
s3:
state = s0;
endcase
end
endmodule
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
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