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This transition diagram can be implemented using a case statement in a process using the following VHDL:
library ieee;
use ieee.std_logic_1164.all;
entity fsm is
port(
Figure 22.1 Hardware state machine structure.
Figure 22.2 State transition diagram.
clk, rst, choice : in std_logic;
count : out std_logic
);
end entity fsm;
architecture simple of fsm1 is
type state_type is ( s0, s1, s2, s3 );
signal current, next_state : state_type;
begin
process ( clk )
begin
if ( clk = 1 ) then
current <= next_state;
end if;
end process;
process ( current )
begin
case current is
when s0 =>
out <= 0;
if ( rst = 1) then
next <= s1;
else
next <= s0;
end if;
when s1=>
out <= 1;
if ( choice = 1) then
next <= s3;
else
next <= s2;
end if;
when s2=>
out <= 2;
next <= s0;
when s3=>
out <= 3;
next <= s0;
end case;
end process;
end;
It must be noted that not all state machines will neatly have a number of states exactly falling to a power of 2, and so unused states must also be managed using the “when-others” approach described elsewhere in this book.
It is also the case that the two processes can be combined into a single process, which can reduce the risk of glitches being introduced by the synthesis tools, especially from incorrect assignments. It can also make debugging simpler.
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