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While the structural approach is useful, it is clearly cumbersome and difficult to configure easily. A more sensible approach is to add a generic (parameter) to the model to enable the number of bits to be customized. For example, if we define an entity to add two logic vectors (as opposed to bit vectors used previously), the entity will look something like this:
library IEEE;
use IEEE.std_logic_1164.all;
entity add_beh is
generic(top : natural := 15);
port (
a : in std_logic_vector (top downto 0);
b : in std_logic_vector (top downto 0);
cin : in std_logic;
sum : out std_logic_vector (top downto 0);
cout : out std_logic
);
end entity add_beh;
As can be seen from this entity, we have a new parameter, top, which defines the size of the input vectors (a and b) and the output sum (cout). We can then use the same original logic equations that we defined for the initial 1-bit adder and use more behavioral VHDL to create a much more readable model:
architecture behavior of add_beh is
begin
adder:
process(a,b,cin)
variable carry : std_logic;
variable tempsum : std_logic_vector(top downto 0);
begin
carry := cin;
for i in 0 to top loop
tempsum(i) := a(i) xor b(i) xor carry;
carry := (a(i) and b(i)) or (a(i) and carry) or (b(i) and carry);
end loop;
sum <= tempsum;
cout <= carry;
end process adder;
end architecture behavior;
This architecture shows how a single process (with sensitivity list a,b,cin) is used to encapsulate the addition. The process is activated when a,b or cin changes. A for loop is used to calculate a temporary sum (tempsum) that increments each time around the loop if required and the final value is assigned to the output sum. Also, a stage by stage carry is calculated and used each time around the loop. After the final loop, the value of carry is used to become the final carry out.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
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Manufacturer:Xilinx
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Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS:
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