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A multiplexer (MUX) is an extension of a simple decoder in that a series of inputs is decoded to provide select enables for one of a number of inputs. In a similar way that n-bits can decode 2 n signals, in a multiplexer, n bits of select line are required to multiplex 2 n signals.
ultiplexers are essential in FPGA internal architectures to select between different implementations of combinatorial logic blocks. For example, consider the simplest multiplexer, a two input (A and B), single output (Q) multiplexer, with a single select line (S).
The IEEE symbol for such a MUX is given in Figure 25.2.
A similar approach to the decoder using the when - else structure can be used to create a simple implementation of the multiplexer, as shown in the following VHDL:
Figure 25.2 Input multiplexer with a single select line.
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity mux21 is
6 port (
7 s : in std_logic;
8 a : in std_logic;
9 b : in std_logic;
10 q : out std_logic
11 );
12 end;
13
14 architecture simple of mux21 is
15 begin
16 q <= a when s = ’0’ else
17 b when s = ’1’ else
18 ’X’;
19 end;
This is an extremely useful model and is extensively used in test structures where it is required to choose between a functional and test input signal input to a flip-flop. The model can be easily extended to accommodate multiple input signals. For example, consider a four input multiplexer, with two select signals (inputs = 2select) and a single output. The VHDL model has largely the same structure, but would look like this:
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity mux41 is
6 port (
7 s : in std_logic_vector (1 downto 0);
8 a : in std_logic;
9 b : in std_logic;
10 c : in std_logic;
11 d : in std_logic;
12 q : out std_logic
13 );
14 end;
15
16 architecture simple of mux41 is
17 begin
18 q <= a when s = "00" else
19 b when s = "01" else
20 c when s = "10" else
21 d when s = "11" else
22 ’X’;
23 end;
Verilog can be used to implement a very similar model, using the select line (s) to define which input (a or b) will be used to set the output (q). The resulting model is shown in the following listing:
1 module mux21(s, a, b, q);
2 output q;
3 reg q;
4 input s;
5 input a;
6 input b;
7
8 always @(s or a or b)
9 begin
10 if ( s == 0 )
11 q = a;
12 else
13 q = b;
14 end if
15 end
16 endmodule
A more elegant way to accomplish the same function is to declare the input choice using an array (d[2]) as shown in the listing following. This is also an extremely scalable way to implement the function, as the size of the input could be defined by a parameter.
1 module mux21b(s, d, q);
2 output q;
3 reg q;
4 input [1:0] d;
5 input s;
6
7 always @(s or d)
8 q = d[s]
9 endmodule
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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