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Registers use a bank of flip-flops to load and store data in a bus. The difference between a basic flip-flop and a register is that, while there is a data input, clock and usually a reset (or clear), there is also a load signal that defines whether the data on the input is to be loaded onto the register or not. The VHDL code for an example 8-bit register would be as follows:
library ieee;
use ieee.std_logic_1164.all;
entity register is
generic (
n : natural := 8
);
port (
d : in std_logic_vector(n−1 downto 1);
clk : in std_logic;
nrst : in std_logic;
load : in std_logic;
q : out std_logic_vector(n−1 downto 1)
);
end entity register;
architecture beh of register is
begin
process (clk, nrst) is
begin
if (nrst = ’0’) then
q <= (others => ’0’);
elsif (rising_edge(Clock) and (load = 1)) then
q <= d;
end if;
end process;
end architecture beh;
This can also use a more indented form of if-then-else structure to separate the check on the clk and the load values as shown here:
library ieee;
use ieee.std_logic_1164.all;
entity register is
generic (
n : natural := 8
);
port (
d : in std_logic_vector(n−1 downto 1);
clk : in std_logic;
nrst : in std_logic;
load : in std_logic;
q : out std_logic_vector(n−1 downto 1)
);
end entity register;
architecture beh of register is
begin
process (clk, nrst) is
begin
if (nrst = ’0’) then
q <= (others => ’0’);
elsif (rising_edge(Clock) then
if (load = ’1’)) then
q <= d;
end if;
end if;
end process;
end architecture beh;
Notice that although there are four inputs (clk, nrst, load, and d), only clk and nrst are included in the process sensitivity list. If load and d change, then the process will ignore these changes until the clk rising edge or nrst goes low. If the load is not used, then the register will load the data on every clock rising edge unless the reset is low. This can be useful in applications such as pipelining, where efficiency is paramount. The VHDL for this slightly simpler register is given here:
library ieee;
use ieee.std_logic_1164.all;
entity reg_rst is
port (
d,
clk,
nrst : in std_logic;
q : out std_logic
);
end entity reg_rst;
architecture beh of reg_rst is
begin
process (clk, nrst) is
begin
if (nrst = ’0’) then
q <= ’0’;
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end architecture beh;
In a similar manner we can write a register model with an input d, load, and nrst control signals, with a clock input and the output q. In this case we use the posedge (positive edge) of the clock and the nest variable as the sensitivity list to the always block.
module register (
d,
clk,
nrst,
load,
q
);
parameter n =8;
input [n−1:0] d;
input clk;
input nrst;
input load;
output q;
reg [n−1:0] q;
always @ (posedge clk or nrst)
if(nrst == 1b’0) then begin
q <= 0;
end
else
if (load == 1b’1) then begin
q <= d;
end
end
endmodule
Manufacturer:Xilinx
Product Categories: Voltage regulator tube
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
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