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In contrast to the level-triggered latch, the flip-flop changes state when an edge occurs on an enable or a clock signal. This is the cornerstone of synchronous design, with an important building block being the D-type flip-flop, as shown in Figure 20.3. The output (Q) will take on
Figure 20.3 D type flflip-flflop.
the value of the input (D) on the rising edge of the clock signal. The triangle on the symbol denotes a clock signal and, in the absence of a circle (notation for active low), the definition is for a rising edge to activate the flip-flop.
The equivalent VHDL code is of the form shown as follows:
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (
d : in std_logic;
clk : in std_logic;
q : out std_logic
);
end entity dff;
architecture simple of dff is
begin
process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end architecture simple;
Notice that, in this case, d does not appear in the sensitivity list, as it is not required. The flip-flop will only do something when a rising edge occurs on the clock signal (clk). There are a number of different methods of describing this functionality, all of them equivalent. In this case, we have explicitly defined the clk signal in the sensitivity list.
An alternative method in VHDL would be to have no sensitivity list, but to add a wait on statement inside the process. The equivalent architecture would be as follows:
architecture wait_clk of dff is
begin
process is
begin
if rising_edge(clk) then
q <= d;
end if;
wait on clk;
end process;
end architecture simple;
This could also be defined using a slightly different implementation of the wait statement, to wait for an event on clk and then check if it was high:
architecture wait_clk of dff is
begin
process is
begin
wait until clk’event and clk = ’1’;
q <= d;
end process;
end architecture simple;
We have also perhaps used a more complex definition of the rising_edge function than is required (or may be available in all simulators or synthesis tools). The alternative simple method is to use the clock in the sensitivity list and then check that the value of clock is 1 for rising edge or 0 for falling edge. The equivalent VHDL for a rising edge D-type flip-flop is given. Notice that we have used the implicit sensitivity list (using a wait on clk statement) as opposed to the explicit sensitivity list, although we could use either interchangeably.
architecture rising_edge_clk of dff is
begin
process is
begin
if (clk = 1) then
q <= d;
end if;
wait on clk;
end process;
end architecture simple;
We can also implement this type of flip-flop using Verilog as shown here:
module dff (
d, / Data Input
clk, / Clock Input
q / Latch Output
);
input d;
input clk;
output q;
reg q;
always @ ( posedge clk )
begin
q <= d;
end
endmodule
We can extend this basic model for a D-type to include an asynchronous set and reset function. If they are asynchronous, this means that they could happen whether there is a clock
Figure 20.4 D-type flflip-flflop with asynchronous set and reset.
edge or not; therefore they need to be added to the sensitivity list of the model. The symbol for such a flip-flop, assuming active low set and reset, would be as shown in Figure 20.4.
The VHDL is extended from the simple dff model previously given to include the asynchronous set and reset as shown in the following:
library ieee;
use ieee.std_logic_1164.all;
entity dff_sr is
port (
d : in std_logic;
clk : in std_logic;
nrst : std_logic;
nset : in std_logic;
q : out std_logic
);
end entity dff_sr;
architecture simple of dff_sr is
begin
process (clk, nrst, nset) is
begin
if (nrst = ’0’) then
q <= ’0’;
elsif (nset = 1) then
q <= ’1’;
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end architecture beh;
As for the basic D type flip-flops, we could use a variation of the check for the clock edge, although due to the fact that we have three possible input state control variables (set, reset, and clk), it is not enough now to check whether the clock is high (for a rising edge flip-flop). It is necessary to check that the clock is high and that an event has occurred.
Notice that this model may cause interesting behavior when synthesized, as the reset will always be checked before the set and so there is a specific functionality that allows the concurrent setting of the set and reset variables, but the reset will take precedence.
We can also implement this behavior in a very similar fashion in Verilog as shown in the following listing:
module dff_asr (
d, / Data Input
s, / Set Input
r, / Reset Input
q / Latch Output
);
input d;
input s;
input r;
output q;
reg q;
always @ ( s or r or clk )
if (~r) begin
q <= 1b’0;
end elseif (s) begin
q <= 1b’1;
else begin
q <= d;
end
endmodule
Finally, when considering the use of transitions between 0 and 1, there are issues with synthesis and simulation when using the different approaches. For example, with the standard logic package (std_logic variables), the transitions are strictly defined and so we may have the case of high impedance or “don’t care” states occurring during a transition. This is where the rising_edge function and its opposite, the falling_edge function, are useful as they simplify all these options into a single function that handles all the possible transition states cleanly.
It is generally best, therefore, to use the rising_edge or falling_edge functions in VHDL (and posed and negedge in Verilog) wherever possible to ensure consistent and interoperable functionality of models.
It is also worth considering a synchronous set or reset function, so that the clock will be the only edge that is considered. The only caveat with this type of approach is that the set and reset signals should be checked immediately following the clock edge to make sure that concurrent edges on the set or reset signals have not occurred.
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