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A latch can be simply defined as a level-sensitive memory device. In other words, the output depends purely on the value of the inputs. There are several different types of latch, the most common being the D latch and the SR latch. First consider a simple D latch as shown in Figure 20.1. In this type of latch, the output (Q) follows the input (D), but only when the Enable (En) is high. The full definition is in fact a level-sensitive D latch, and the assumption made in this book is that whenever we refer to a latch, it is always level sensitive. It is worth noting that latches are not particularly useful in FPGA design as they are obviously asynchronous and therefore can cause timing issues. In practice it is much better to use synchronous D-types, as will be introduced later in this chapter; however, it is worth looking at basic latches to see the differences.
The notation on the Enable signal (C1) and the Data input (1D) denotes that they are linked together. Also notice that the output Q is purely dependent on the level of D and the Enable. In other words, when the Enable is high, then Q = D. So, as previously stated, this is a level-sensitive latch.
The VHDL that represents this kind of level-sensitive D latch is shown here:
library ieee;
use ieee.std_logic_1164.all;
entity latch is
port (
d : in std_logic;
Figure 20.1 Basic D latch symbol.
en : in std_logic;
q : out std_logic
);
end entity latch;
architecture beh of latch is
begin
process (d, en) is
begin
if (en = ’1’) then
q <= d;
end if;
end process;
end architecture beh;
We can implement a very similar model using Verilog with the code given following this paragraph. In this case the Verilog uses the always statement to check for any changes on the enable or the d inputs and if enable (en) is high, then the output will also change.
module dlatch (
d, / Data Input
en, / Enable Input
q / Latch Output
);
input d;
input en;
output q;
reg q;
always @ ( en or d )
if (en) begin
q <= d;
end
endmodule
This is an example of an incomplete if statement, where the condition if(en = 1) is given, but the else condition is not defined. Both d and en are in the sensitivity list and so this could be combinatorial, but due to the incomplete definition of en, then an implied latch occurs, that is, storage. This aspect of storage is important when we are developing models, particularly behavioral as in this case (i.e., the structure is not explicitly defined), as we may end up with
Figure 20.2 Synthesized latch.
latches in our design even though we think that we have created a model for a purely combinatorial circuit.
Other instances when this may occur are the incomplete definition of case statements. For example, consider this simple VHDL example:
case s is
when "00" => y <= a;
when "10" => y <= b;
when others => null;
end case;
In this statement, it is incomplete and so instead of a simple combinatorial circuit, a latch is therefore implied. The resulting synthesized circuit is shown in Figure 20.2.
Similar outcomes would happen if a Verilog case statement was incomplete:
case s is
2’b00 : y=a;
2’b10" : y=b;
end case;
In both cases it is important to ensure that all the states are defined to avoid this happening, and in Verilog this is done by using the default option in the case statement. Therefore, in our simple example, to ensure that all the possible values of s are covered, the default line will specify an output in those cases as shown here:
case s is
2’b00 : y=a;
2’b10" : y=b;
default : y=0;
end case;
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