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The Johnson counter is a counter that is a simple extension of the shift register. The only difference between the two is that the Johnson counter has its least significant bit inverted and fed back into the most significant bit of the register. In contrast to the classical binary counter with 2n states, the Johnson counter has 2 n states. While this has some specific advantages, a disadvantage is that the Johnson counter has what is called a parasitic counter in the design. In other words, while the 2 n counter is operating, there is another state machine that also operates concurrently with the Johnson counter using the unused states of the binary counter. A potential problem with this counter is that if, due to an error, noise or other glitch, the counter enters a state NOT in the standard Johnson counting sequence, it cannot return to the correct Johnson counter without a reset function. The normal Johnson counter sequence is shown in the following table:
The VHDL implementation of a simple Johnson counter can then be made by modifying the next stage logic of the internal shift_register function as shown in the following listing:
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 entity johnson_counter is
5 generic (
6 n : integer := 4;
7 port (
8 clk : in std_logic;
9 rst : in std_logic;
10 din : in std_logic;
11 q : out std_logic_vector((n−1) downto 0)
12 );
13 end entity;
14
15 architecture simple of Johnson_counter is
16 begin
17 process(clk, rst)
18 variable j_state : std_logic_vector((n−1) downto 0);
19 begin
20 if rst = ’0’ then
21 j_state:= (others => ’0’);
22 elsif rising_edge(clk) then
23 j_state:= not j_state(0) & j_state(n−1 downto 1);
24 end if;
25 q <= j_state;
26 end process;
27 end architecture simple;
Notice that the concatenation is now putting the inverse (NOT) of the least significant bit of the internal state variable (j_state(0)) onto the next state most significant bit, and then shifting the current state down by one bit.
It is also worth noting that the counter does not have any checking for the case of an incorrect state. It would be sensible in a practical design to perhaps include a check for an invalid state and then reset the counter in the event of that occurrence. The worst-case scenario would be that the counter would be incorrect for a further 7 clock cycles before correctly resuming the Johnson counter sequence.
In a similar manner we can implement a Johnson counter in Verilog using the code given here:
1 module johnson_counter (
2 clk, / clock input
3 rst, / reset (active low)
4 johnsonreg / shift register
5 );
6
7 input clk;
8 input rst;
9
10 output [7:0] johnsonreg;
11
12 wire clk;
13 wire rst;
14
15 reg [7:0] johnsonreg ;
16
17 always @ (posedge clk)
18 begin : count
19 if (rst == 1’b0) begin
20 johnsonreg <= #1 4’b00000000;
21 end
22 else begin
23 johnsonreg <= #1 {!johnsonreg[0], johnsonreg[7:1]};
24 end
25 end
26
27 endmodule
Figure 24.6 Johnson counter simulation.
and test it using the same basic counter test bench created for the simple counter, giving the simulation results as shown in Figure 24.6. We can see that the counter variable “ripples” through till it gets to all 1s and then carries back on until it is all 0s.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Any -
RoHS:
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