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At this point it is useful to consider what happens when we synthesize this VHDL, so to test this point the VHDL model of the simple binary counter was run through a typical RTL synthesis software package (Leonardo Spectrum) with the resultant synthesized VHDL model given here:
Figure 24.3 Simple binary counter simulation in Verilog.
1 entity counter is
2 port (
3 clk : IN std_logic ;
4 rst : IN std_logic ;
5 output : OUT std_logic_vector (3 DOWNTO 0)) ;
6 end counter ;
7
8 architecture simple of counter is
9 signal clk_int, rst_int, output_dup0_3, output_dup0_2, output_dup0_1,
10 output_dup0_0, output_nx4, output_nx7, output_nx10, NOT_rst,
11 output_NOT_a_0: std_logic ;
12
13 begin
14 output_obuf_0 : OBUF port map ( O=>output(0), I=>output_dup0_0);
15 output_obuf_1 : OBUF port map ( O=>output(1), I=>output_dup0_1);
16 output_obuf_2 : OBUF port map ( O=>output(2), I=>output_dup0_2);
17 output_obuf_3 : OBUF port map ( O=>output(3), I=>output_dup0_3);
18 rst_ibuf : IBUF port map ( O=>rst_int, I=>rst);
19 output_3_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_3, D=>output_nx4,
20 C=>clk_int, CLR=>NOT_rst);
21 output_2_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_2, D=>output_nx7,
22 C=>clk_int, CLR=>NOT_rst);
23 output_1_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_1, D=>output_nx10,
24 C=>clk_int, CLR=>NOT_rst);
25 output_0_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_0, D=>
26 output_NOT_a_0, C=>clk_int, CLR=>NOT_rst);
27 clk_ibuf : BUFGP port map ( O=>clk_int, I=>clk);
28 output_nx4 <= (not output_dup0_3 and output_dup0_2 and output_dup0_1 and
29 output_dup0_0) or (output_dup0_3 and not output_dup0_0) or (output_dup0_3
30 and not output_dup0_2) or (output_dup0_3 and not output_dup0_1) ;
31 output_nx7 <= (output_dup0_2 and not output_dup0_0) or (not output_dup0_2
32 and output_dup0_1 and output_dup0_0) or (output_dup0_2 and not
33 output_dup0_1) ;
34 output_nx10 <= (output_dup0_0 and not output_dup0_1) or (not
35 output_dup0_0 and output_dup0_1) ;
36 NOT_rst <= (not rst_int) ;
37 output_NOT_a_0 <= (not output_dup0_0) ;
38 end simple ;
The first obvious aspect of the model is that it is much longer than the simple RTL VHDL created originally. The next stage logic is now in evidence; as this is synthesized, the physical gates must be defined for the model. Finally the outputs are buffered, which leads to even more gates in the final model. If the optimization report is observed, the overall statistics of the resource usage of the FPGA can be examined (in this case, a Xilinx Virtex-II Pro device):
Cell Library References Total Area
========================================================
BUFGP xcv2p 1 x 1 1 BUFGP
FDC xcv2p 4 x 1 4 Dffs or Latches
IBUF xcv2p 1 x 1 1 IBUF
LUT1 xcv2p 2 x 1 2 Function Generators
LUT2 xcv2p 1 x 1 1 Function Generators
LUT3 xcv2p 1 x 1 1 Function Generators
LUT4 xcv2p 1 x 1 1 Function Generators
OBUF xcv2p 4 x 1 4 OBUF
Number of ports : 6
Number of nets : 17
Number of instances : 15
Number of references to this view : 0
Total accumulated area :
Number of BUFGP : 1
Number of Dffs or Latches : 4
Number of Function Generators : 5
Number of IBUF : 1
Number of OBUF : 4
Number of gates : 5
Number of accumulated instances : 15
Number of global buffers used: 1
***********************************************
Device Utilization for 2VP2fg256
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 5 140 3.57%
Global Buffers 1 16 6.25%
Function Generators 5 2816 0.18%
CLB Slices 3 1408 0.21%
Dffs or Latches 4 3236 0.12%
Block RAMs 0 12 0.00%
Block Multipliers 0 12 0.00%
In this simple example, it can be seen that the overall utilization of the FPGA is minimal, with the relative resource allocation of IOs, buffers and functional blocks. This is an important aspect of FPGA design in that, even though the overall device may be underutilized, a particular resource (such as IO) might be used up. The output VHDL can then be used in a physical place and route software tool (such as the Xilinx Design Navigator) to produce the final bit file that will be downloaded to the device.
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Industrial components
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
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