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With the same basic specification as the VHDL counter, it is possible to implement a basic counter in Verilog using the same architecture of the model.
1 module counter (
2 clk, / clock input
3 rst, / reset (active low)
4 counter_output / counter output
5 );
6
7 input clk;
8 input rst;
9
10 output [3:0] counter_output;
11
12 wire clk;
13 wire rst;
14
15 reg [3:0] counter_output ;
16
17 always @ (posedge clk)
18 begin : count
19 if (rst == 1’b0) begin
20 counter_output <= #1 4’b0000;
21 end
22 else begin
23 counter_output <= #1 counter_output + 1;
24 end
25 end
26
27 endmodule
The model has the same connection points and operation, and will be treated in the same way for synthesis by the design software. The test bench is slightly different from the VHDL one in that it is much more explicit about the test function as well as the functionality of the test bench. For example, if we look at the top of the test bench Verilog has the $display and $monitor commands, which enable the time and variable values to be displayed in the monitor of the simulation as well as looking at the waveforms.
1 $display ("time\t clk reset counter");
2 $monitor ("%g\t %b %b %b",
3 $time, clk, rst, counter_output);
Using this test bench and Verilog model the behavior of the simulation can also be verified as shown in Figure 24.3.
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Module RF, IC et Accessoires
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
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