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Timing paths are defifi ned by the connectivity between the instances of the design. In digital designs, timing paths are formed by a pair of sequential elements controlled by the same clock or by two different clocks.
In order to debug and fifi x the timing paths, it is important to fifi rst check whether these paths are valid or not. Checking constraints is one of the key and easy steps in getting to timing closure. One of the common issues in writing of XDC constraint is related to incorrect cross- clock domain crossing paths. Timer takes the worst case requirements for timing analysis. Hence if cross-clock paths are getting wrongly timed (very often they needn’t be timed), they might have very tough requirement, resulting in a big negative slack. Report CDC and report clock interaction are two very useful commands to check if the interclock paths are being timed correctly.
Clock Interaction
Report clock interaction gives a matrix and specififi es where all the clock pairs in the design are considered for interaction. Each entry in the matrix is color coded. All the entries across the diagonal are the paths within the same clock group. It is important to examine if there are any unexpected cross-clock domain paths, and fifi x them by adding proper XDC constraints ( set_false_path , set_clock_groups ). Xilinx published UG903 has more details.
Report Clock Domain Crossing
Report CDC (clock domain crossing) performs a structural analysis of the clock domain crossings in your design. You can use this information to identify potentially unsafe CDCs, which will lead to metastability or data coherency issues. While the CDC report is similar to the clock interaction report, the CDC report focuses on structures and their timing constraints, but does not provide information related to timing slack.
Before generating the CDC report, you must ensure that the design has been properly constrained and there are no missing clock defifi nitions. Report CDC only analyzes and reports paths where both source and destination clocks have been defifi ned. Report CDC performs structural analysis on:
1. On all paths between asynchronous clocks
2. Only on paths between synchronous clocks that have the timing exceptions (e.g., clocks coming out of MMCM)
Synchronous clock paths with no such timing exception are assumed to be safely timed and are not analyzed by the CDC engine. The report CDC operates without taking into consideration any net or cell delays.
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
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Product Categories: FPGAs (Field Programmable Gate Array)
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