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Generating Timing Reports
The fifi rst step in timing closure is to understand whether the design has met all the timing checks or not. In order to generate timing reports to view failing paths, the following options are available in Vivado.
Report Timing Summary
Report timing summary gives an overall picture of timing on the design. It performs setup , hold , pulse-width checks, and gives a summary on whether some or all of these checks have failed. Even if one of the checks has failed, this command reports that the design has failed to meet timing. Based on this report, it can be decided if further steps are needed to achieve timing closure. Figure 14.1 gives a sample snap shot of the command, where setup , hold , and pulse-width violations are checked.
Once the design is determined to have not met timing requirements, you can further analyze failing timing paths in the design by running report timing or slack histogram command.
Report Timing
Report timing summary only gives a top-level report on timing failures; however, report timing gives details of all the paths that fail timing checks (setup and hold). By default report timing reports on all path groups and prints the top 10 paths in each path group and sort it by slack in ascending order. Additional fifi lters can be added to customize timing analysis on different from , through , or to points as well as select more paths to view. Report timing only works for setup and hold checks. Pulse-width checks are reported in Vivado log fifi le indicating where the errors are.
Slack Histogram
Another way to see the failing timing paths is to generate slack histogram . Slack histogram gives a concise view of all the timing paths across all path groups. Figure 14.2 shows a sample slack histogram plot. Slack histogram divides the slacks into different bins. The X -axis represents different slack bins and the Y -axis represents the number of paths in each bin. Clicking on each of the bars fifi lters the paths in that bin, where you can examine paths in each of the bin.
In both report timing and slack histogram, you can click and double-click any of the paths to examine each of the timing path in detail, including characteristics of the path as well as placement and connectivity details.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
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