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SSI Synthesis Techniques
Once the SLR partitioning has been decided, creation of the design can commence. Design entry does not have to differ from that of a monolithic design creation. Functional verififi cation is also no different. Synthesis and implementation may be augmented to help with this design flfl ow. There are three possible approaches to synthesis for a manually partitioned design. In all of these synthesis approaches, the common theme is maintaining designated SLR partitions during the design flfl ow which should maintain the intended data paths between SLRs.
Top-Down Synthesis
One method is to use a standard top-down approach. For the instances at SLR partition boundaries, place KEEP_HIERARCHY attributes. The KEEP_HIERARCHY attribute as the name implies instructs synthesis to retain the hierarchy in which it is applied which limits optimization at and across that hierarchy. Using this attribute prevents synthesis from moving intended logic from one hierarchy boundary to another and should retain all logic structures including additional pipelining at that boundary. Strategically placing this attribute only on the hierarchy instances that border an SLR allows synthesis to optimize across logical hierarchies contained solely within an SLR while preventing optimization of logic across designated SLRs.
Bottom-Up Synthesis
This approach generally consists of synthesizing each SLR or portions of SLR logic in its own separate project. This methodology by design will prevent optimization of logic across the designated boundaries but also can help facilitate team design by allowing multiple portions of the design to be implemented and verififi ed in parallel. This method also does the best job to retain the results of areas of the design that have not changed from iteration to iteration. There are other benefifi ts such as the ability to apply unique synthesis options for each portion of the design, and often overall runtime between iterations is reduced with this method. The drawbacks are that multiple synthesis projects must be maintained, and design coordination and assembly could become a little more diffifi cult compared to the top-down approach.
OOC Synthesis
Yet another method that you could use is to synthesize the designated SLR partitions out of context with each other. This design methodology is a hybrid approach in that a single project can be maintained; however, the individual SLR partitions can be implemented independent of each other and later assembled when the toplevel of the project is implemented.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Any -
RoHS: -
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
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