Partitioning Considerations

Partitioning Considerations

For automatic partitioning, there is no difference in how you would operate the tools over targeting a traditional monolithic device. Manual partitioning however involves more up-front planning. Logical hierarchical boundaries, selected IP, division of design between different engineering teams, or combination of these factors are used to decide what logic should be physically placed in which SLR. The mechanics of manual partitioning is not all that different from flfl oor planning, which is a common design closure technique.

Limit SLR Crossings

There is a relatively high but hard limit in the number of signals that can cross from one SLR to another, so ensure that any selected partition does not exceed the available SLL s for the selected device. Make an effort to understand the number of available SLLs per-SLR crossing as well as the expected SLLs required by the design as criteria in selecting a partition. The example in Sect. 13.3 showed that the number of SLR crossings is often dictated by the dataflfl ow of the design. So, good pinout selection is important. Once the dataflfl ow of the design is established, the mapping of the associated logic to those datapaths is often a much simpler task. After decisions as to which logic hierarchies should be mapped into which SLRs, the number of SLR crossing required for the design can be tallied and tracked. In general avoid using more than 60 % of the given SLLs in the device for any given SLR crossing. The reason behind this is twofold. Higher utilization of SLLs requires more tradeoffs for placement and routing of those SLR crossing, and since the SLR crossing can often be critical paths in the design, building additional flfl exibility for placement can pay large benefifi ts for timing closure. The other reason to reduce utilization is to allow future design changes and additions without concern for overutilization of SLL resources.

Report Design Analysis has a section that provides information on modules that are contributing to SLR crossings. This can help you in making decisions related to flfl oor planning—by blocking this module to an SLR—if possible.

On the other hand, keep in mind that trying to reduce the number of SLR crossings could cause you to place more and more logic within an SLR—causing higher utilization within the SLR. Hence, it is good to maintain a good balance.

Limit Timing Critical Paths Across SLRs

Where possible, pipeline the data paths for the SLR crossings. If it becomes necessary to have signals that cross multiple SLRs, add additional pipeline stages accordingly to ensure adequate timing margin for such crossings. Making the decision up-front as to pipeline these interfaces often makes it much easier to understand and balance the pipeline stages compared to adding it in later stages of the design. A good practice is to use a common naming convention for registers intended for SLR interface crossing as it can help with timing analysis and flfl oor planning later. It may also be necessary to add synthesis attributes on these pipeline registers to prevent synthesis from using shift register LUTs for those structures when multiple pipeline stages are used in a single SLR. When possible, locate control logic and the associated control signals from the data paths in the same SLR. For control logic that must span multiple SLRs, it is often best to place the logic into a centralized SLR to the partitioned logic in order to allow a more evenly distributed timing. If it is suspected that timing may still be critical, replication of the logic may become necessary in order to best manage locating the source logic to its loads. This is not much different from the process used in monolithic design. The only difference is that these decisions now have ramififi cation into the partitioning decisions for the logic.

Balance Resource Usage

Resource management is important whether using automatic partitioning or manual partitioning; however, manual partitioning adds the extra task of determining a proper balance of those resources across the different SLRs. It should be planned so that any one SLR does not become too full as to negatively impact place and route results. The actual target for maximum resource usage depends on the resource type, performance requirements, and the interaction between them. For instance, a design which has a lot of margin for performance may be able to fifi ll the SLRs to a larger capacity than one that can barely meet timing with the current requirements and design characteristics. Also, often larger blocks such as RAM blocks or DSP blocks are more diffifi cult to get higher utilization within the SLR than more common blocks like LUTs or registers. An effective strategy for designs requiring a high percentage utilization of a particular resource is to trade off for another. For instance, if a particular design requires a high percentage of block memory, utilizing a lesser amount of LUTs and DSP often helps in the overall place and route results. Another consideration is future design growth. A good partitioning plan accounts for areas of the design that may grow so that as the design defifi nition changes, the partitioning does not need to change to account for that.

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