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Pinout Considerations for SSI Designs
Another important up-front consideration is the pinout selection. Whether using an automatic or manual partitioning style, selection of which I/O pins are located in which SLR has a substantial impact on the associated logic placement and routing of the design. A well thought-out pinout selection will lead to good dataflfl ow through the FPGA leading to good implementation results, providing better utilization, timing, and power. The best approach to determine a good pinout starts with examining the expected dataflfl ow of all portions of the design and how that maps to the I/O resources of the device. All associated control signals such as clocking, enables, and resets should be considered in conjunction with this data flfl ow.
The data path represented in Fig. 13.2 originates at SLR 0 (bottom SLR), must go to the SLR 3 (top SLR) in order to buffer the data to an external memory, and then travel back to SLR 1 to exit the device. This pinout selection has some obvious drawbacks. First off, the data path is required to traverse six SLRs to complete the data cycle. This could cause possible timing and resource issues. Also notice that the clock and reset signals that must drive all of the logic are located in SLR3. Since
these are high fanout signals, a better selection would be in the center SLRs so that the signals can be more evenly distributed improving the overall timing paths of both signals. Placing the reset in the center would likely reduce the overall delay from source to destination as the overall distance between these points is minimized. Moving the clock to a more centralized location will also reduce the insertion delay but, more importantly, it balances the overall clock skew as well. With the clock placed in the top SLR, the data path entering the chip to the external memory interface must travel against the clock. This increases the amount of negative clock skew for that portion of the path resulting in reduced timing margin. The best placement for the clock has to do with what portion of the design is expected to have the least timing margin and placing the clock so that it is either in the same SLR or the clock travels with the data. Having the clock travel in the same direction as data will improve setup timing margin by making use of useful (positive) skew.
Figure 13.3 shows the same data path with the memory interface moved to SLR1 and the clock and reset relocated to SLR0. The benefifi ts of this change should be fairly evident. The overall SLR crossings reduced from 5 to 1. The high fanout reset now only needs to reach two SLRs rather than all four and is located closer to the logic it must drive. The clock is placed in SLR 0 so that the overall data path is traveling with the clock rather than against it, promoting better skew characteristics for this path. This pinout will likely consume less routing and fewer logic resources as less pipelining and resource impacting optimizations like logic replication should be necessary. Such simple pinout changes could have a dramatic impact on the over all implementation results of this design.
Often pinout decisions must weigh a balance between board layout considerations and internal dataflfl ow optimization. Due to the size of SSI device packages, often there are numerous high-speed connections that must be routed out of a dense ball grid array that pose its own diffifi culties in PCB routing and power delivery. This
often leads to an iterative approach between the digital design team and the printed circuit board team trying to fifi nd the best compromise between internal dataflfl ow and external PCB routability. Extra time and effort spent at this point can pay large dividends later in terms of easing design timing closure and reducing the overall design implementation cycle while also requiring fewer device resources and less power consumption as once pinout decisions are fifi xed, it is very diffifi cult to change later.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
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