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Design Partitioning
One of the fifi rst SSI-specififi c decisions is to either chose to manually select or partition the logic to each underlying SLR in the device or to allow the tools to automatically partition the design into the separate SLRs. Vivado has the ability to take a single defifi nition of the design and decide what portions of the logic should be placed into which SLR. The primary benefifi t of automatic partitioning is the obvious up-front ease-of-use benefifi t of not having to make such a decision, and it is very possible that you may see better out-of-the-box performance and results from automatic partitioning. Automatic partitioning can also result in higher device utilization and can potentially adjust to signififi cant design changes more easily than manual partitioning. The drawback however is the loss of control of the design placement in the FPGA which may yield less repeatability and control during timing closure. In situations where timing closure may prove diffifi cult, this may be a very important trade- off to consider as the added control may allow much quicker timing closure for diffifi cult designs.
The primary design parameter that often dictates the better flfl ow has to do with performance requirements and how much margin there is in the design to meet those requirements. For designs that wish to push the limits of the device in terms of performance or for designs in which it is desired to ensure that areas of the design that remain unchanged to have similar place and route results in future runs, manual partitioning is generally the better choice. An important thing to note is that performance limits are not always dictated by desired clock rate. For instance, for a design that has low latency or lack of pipelining, several logic levels or high fanout nets may have a much lower maximum clock rate than one that is highly pipelined. For this example, a much lower clock frequency may be pushing the performance limits of the device compared to that of a well-crafted, pipelined version operating in that same device. Following good overall design practices promotes more performance margin in the device in general and can lead to more flfl exibility in such design decisions. The main thing to consider is how much performance margin is expected for the design. For designs that have adequate performance margin, either method (manual flfl oor planning or auto derived) may be suitable.
Manufacturer:Xilinx
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
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Lifecycle:Any -
RoHS: -
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