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Home > FPGA Technical Tutorials > Designing with Xilinx FPGAs Using Vivado > Clocking > Optimizing Clock Networks for Interfaces

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Optimizing Clock Networks for Interfaces

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GT Clocking

GT clocking is generally taken care of by the IP. However, there are use cases where  proprietary protocols need implementing, and in this case clocking should be  understood. In UltraScale, MMCMs and PLLs are generally not required for GTs.  This makes the clocking much more scalable to the GT count. Instead, dividers in  BUFG_GT allow a user to generate the user clocks to interface with the GT. Typically   USRCLK 1 and USRCLK2 are either frequency matched or USRCLK2 is half the  rate of USRCLK1. The choice of this depends on the protocol.

Additionally there are some protocols that require a line rate change. Line rate  changes also require a USRCLK change that is in proportion to the line rate change.   BUFG_GTs provide a user signal divide capability that allows a user to change the  divide ratio of the input/output clock. Synchronization logic is also provided to  allow a seamless clocking change.

IO Interfaces

Only use a MMCM for system synchronous IO interfaces. PLLs do not provide  clock network deskew. Generally for interfaces, use MMCM CLKOUT0 and set  compensation to ZHOLD . For source synchronous interfaces, MMCM can be used  but setting for ZHOLD may adversely impact timing. You should play with the  options here to establish good timing. Good constraints are mandatory for this  approach.


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