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Optimizing Clock Networks to Improve Internal Timing
Vivado models the most pessimistic timing. That means for setup analysis, the source path will have maximum delay, while destination path will have minimal delays. These conflfl icting models can signififi cantly reduce timing budget but are required to generate a design that works in hardware in all devices.
Clock Pessimism Removal and the Common Node
Clock pessimism removal is compensation in a timing report for the common segments in the clock paths. It is not possible to have both the best and worst case occurring at the same time, on any given path segment. Vivado compensates for the unnecessary pessimism due to delay differential on this common segment. The point at which the source and destination clocks diverge is termed the common node , as shown in Fig. 12.8 . Having the common node as close as possible to both the source and destination will improve timing margin signififi cantly as signififi cant portion will be common, from where pessimism would be compensated.
You can inflfl uence common node during early clocking decisions, such as clock frequency to use. If you choose a common clock, the common node will be somewhere after the BUFG. If you choose different clocks, then the common node will
be at the MMCM. If you opt for different clocks, then consider using asynchronous design techniques to cross the clock boundaries to improve timing. Using, for example, a FIFO will mean that timing can be relaxed at this point.
Minor common node inflfl uences, such as different slices, are largely controlled by the placer. However, if manually creating a flfl oor plan, keep to clock region boundaries for optimal common nodes. Horizontal flfl oor plan shapes are more optimal than vertical ones but, sometimes, some other considerations (e.g., data flfl ow through DSP chain) may cause you to prefer vertical shapes.
Optimizing Common Node for Synchronous Cross Domain Crossings
In UltraScale, the total length of a typical clock network is made up of MMCM → BUFG → CLOCK_ROOT → LOADs. When crossing between two different clocks, the common node will be at the MMCM/PLL, as shown in Fig. 12.9
In the case where the MMCM is not required for IO interfaces, it can be optimal to move the MMCM/BUFGs as close to CLOCK_ROOT as possible, as shown in Fig. 12.10 . This has the effect of improving the common node, and hence greater clock pessimism removal is seen. An initial run through the tools is required to achieve this optimization.
In order to do this optimization, you must instruct Vivado as the default is to have the MMCM next to the global clock input, through the following:
1. LOCK the MMCM to the clock region close to the CLOCK_ROOT.
2. Insert a BUFGCE between the IO and the MMCM.
Phase Error
When two clocks come out of the same MMCM and there are timing paths between them, a value for phase error is added to both setup and hold times. This value is 120 ps for both windows. Together this creates a window of at least 240 ps that reduces timing margin. In reality, when common node compensation and hold time fifi xing are added, approximately 1200 ps are lost from the setup window. This should be taken into account when crossing between related clocks.
Internally Related Clocks Divisible by 2, 4, and 8
In a special case where the clocks are multiple of each other, use BUFGCE_DIV from a single output of MMCM/PLL. This will remove phase_error and improve the common node .
BUFGCE_DIV primitives can divide the clock by an integer number between 1 and 8. Since there are four BUFGCE_DIVs in a region, you can derive up to four divided clocks. Consider the example circuit shown in Fig. 12.2 . The clocking can be improved as shown in Fig. 12.11 . The key steps are:
• Generate an MMCM with just the highest frequency output, in this case CLK2X. The Clocking Wizard IP should use no buffer as its drives selection
• Connect up 3 BUFGCE_DIV buffers in parallel
• Even for the original clock, insert a BUFGCE_DIV to divide-by 1, which helps achieve uniform delay in the clock paths
%20Alternate%20combination%20of%20output%20jitter.png "One combination of output jitter values. ( b ) Alternate combination of output jitter.png")
Jitter Reduction
Jitter can be reduced by selecting different options in the Clocking Wizard IP. Output jitter can be minimized at the expense of input jitter fifi ltering. It is recommended to play with these options and evaluate the output under the Port Renaming tab inside the Clocking Wizard . It is possible to improve each path in the design by up to ±150 ps by selecting optimal settings. Figure 12.12a, b shows two difference values for peak-to-peak jitter for outputs, using two different settings ( balanced and output jitter optimized , respectively). Be aware that change in these jitter values could impact power also, because higher frequency of VCO will result in higher power.
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