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Choice of Clock Frequency
A typical FPGA design has many clock networks, as shown in Fig. 12.1 , because each of the following may have its own network:
each of the following may have its own network:
• Each source synchronous interface coming into or leaving the FPGA
• Each transceiver interface
• Internal system FPGA clock network
• Low-speed clocking networks for control like high fanout processor control via an AXI-Lite interface, external flfl ash clocking
• Optional internal fast clock networks for conducting DSP operations
Most designs do not run at any single clock frequency. Design frequencies are normally dictated by:
• Bandwidth of incoming data
• Bandwidth of outgoing data
• Resource consumed by a particular function
The fifi rst two points are typically decided by the system. However, the third point is a design decision, in the sense that there might be multiple combinations of freq vs. utilization that would be possible. Generating different frequency clocks is easy in a FPGA. Running something faster will usually save resource. So, you can change frequency to save FPGA resource like DSP slices.
Wireless radio designs, for example, have parts that run at sweet spot frequency of 491 MHz. Usually it is only the DSP portions that run at this performance. This includes fifi lters, power monitors, DPD, and crest factor reduction. The designs have characteristics such as:
• Low load control paths.
• Point-to-point data paths.
• Design can be pipelined without issue.
• Data paths are typically small around 32 bits.
Wired designs tend to have a lot of switching and wide data paths. Data paths can be 512/1024/2048 bits. These large data paths represent a challenge to the FPGA design software. You can help here by selecting a frequency that balances the diffifi culty and data path width. These designs tend to operate in the region of 300–350 MHz. For UltraScale+, there could be benefifi t in doubling the frequency to something like 600 MHz and halving the data width. Smaller data widths are easier to route for the FPGA software tools.
For other types of design, you should consider data path sizes , high fanout nonclock nets, and logic levels required. These are the typical factors that inflfl uence Fmax . Of course, faster device families and speed grades move the window.
You should also consider productivity against the cost saving of running faster. It is important to choose the right performance without impacting your productivity level. For example, closing timing at 400 MHz may take a few extra weeks compared to closing timing at 200 MHz.
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