Vivado Report Power

Report Power is a very detailed power analysis tool and computes power at a fifi negrained level. For example, it estimates power for each LUT based on switching activity and capacitance information present at input and output pins of the LUT . Similarly, it accounts for the exact routing of each net while estimating power. This is in contrast to the coarse model present in XPE.

The Vivado Power Analysis engine uses four types of information as shown in Fig. 15.2 . It gathers the netlist information and configurations of various blocks by analyzing the design. It uses hardware characterization data based on selected device and package. Operating conditions like process, voltage, and temperature must be set and are typically pre-decided when exploring through XPE. Finally, power constraints comprising of switching activity constraints and clock constraints need to be carefully set to get accurate power estimation. All these are passed as inputs to various algorithms to come up with a detailed power estimation.

Vivado power analysis engine

Operating Conditions

Defifi ning proper operating conditions are essential for the accuracy of power calculations. Power engine can use predefifi ned typical or calculated values for most of the operating conditions; however, it is strongly recommended that you overwrite a few critical values based on the system specififi cations. For example, if you are aware of the maximum junction temperature, then you should set that in operating conditions. This will prevent the tool from estimating junction temperature based on environment and board setup. Similarly, the tool default for the process corner is typical. You should change this to maximum to get worst-case device static power. You should also provide exact or worst-case (i.e., maximum) supply voltage values provided by external power regulators as power depends signififi cantly on voltage supply values.

Power Constraints

Similar to static timing analysis (STA) tools, Vivado Power Analysis (report power) requires you to provide power constraints to guide the tool for accurate power prediction. Power constraints are specififi c to clock frequency and switching activities. For clocks, the frequency can be constrained using the same SDC timing commands. You need to guarantee that all the clocks are properly constrained. Switching activity is represented by a pair of values as ( toggle_rate, static_probability ). By defifi nition, toggle_rate is the probability of a signal in a synchronous design making a ‘0’ → ‘1’ or ‘1’ → ‘0’ transition within a clock cycle. Static_probability is the probability of a signal being 1 in any clock cycle. Figure 15.3 shows signal x with toggle_rate of 40 % and static_probability of 0.3 within a ten clock-cycle window.

Power analysis requires switching activities for all nets. At the fifi rst appearance, this seems like a daunting task for users to provide all switching activity constraints in brute force. The novel methodology in Vivado Power Analysis requires you to only provide switching activities for a subset of nets rather than all of them and, together with the activity propagation engine (see Sect. 15.3.3 ), greatly minimizes design effort and at the same time provides accurate results. There are two ways to provide switching activity information.

First, you can simulate the design (or its portions) to generate switching activity constraints. It is recommended that you do simulation on some critical modules of the design and generate a Switching Activity Interchange Format ( SAIF ) fifi le. This fifi le can then be used to annotate switching activities on the design. Power results are greatly impacted by simulation done at different design stages as well as with or without glitches. For accuracy purpose, simulation at post route stage with delays will generate switching activities most close to real hardware.

Second, if simulation results are not available, you can constrain critical control signals of the design and let activity propagation engine estimate activities on the remaining nets. The critical control signals are those that can enable or disable a large portion of the design. Examples of critical control signals include set/reset pins that drive large flfl op fan-outs, block RAM enable pins that switch on/off the data path, clock selection pins to switch between clocks at clock controller output, pins that enables the power down or sleep feature of hard IP blocks, etc. Not all control signals are critical. Control signals that only reset limited number of nonessential flfl ops can be safely ignored without impacting the accuracy of power prediction.

e safely ignored without impacting the accuracy of power prediction. In addition to critical control signals, another way of guiding the tool is to provide activities on groups of data path signals, for example, block RAM or GT data output pins and chip-level input ports. This approach of setting activities en masse is useful in doing worst-case power estimation.

Activity Propagation

After constraints are provided to annotate partial design nets with switching activities, activity propagation engine triggers to propagate activities on the remaining parts of the design. The activity propagation is a statistical analysis based engine and, on a large design with a million LUTs and registers, can usually complete within several minutes. Figure 15.4 demonstrates activity propagation for a simple AND gate

Assume the same static_probability for input a and input b : SP(a) = SP(b) = 0.5. Those values can be from user constraints or propagated values from previous logic. In the case of the AND gate, SP(o) is computed to be 0.5 × 0.5 = 0.25. This is under the assumption that inputs a and b are totally independent of each other. Similarly, activity propagation engine will also compute output toggle rate. Details of this algorithm are not necessary for you as a user of these tools. Not just combinational circuits, activity propagation engine can also propagate activities across sequential circuits.

Real designs are usually large and complex due to correlations between different signals. It is infeasible to compute exact switching activity for all the nets within a

AND gate.png

reasonable amount of time. Report Power activity propagation engine is able to intelligently solve a subset of correlations in the design and trades off between runtime and accuracy. With proper constraints on clocks and critical control signals, Report Power is able to predict power reasonably close to hardware measurement. It is to be noted that activity propagation engine does not override user-provided constraints, rather it uses them as inputs to estimate activities on remaining nets. Because of its ease of use over other activity analysis methods like simulation, activity propagation can be used to effifi ciently evaluate relative impact on power after a design netlist change or switching activity change.

Export– Import Flow with XPE

Vivado Report Power and XPE are two independent power analysis tools. In Report Power , majority of the information is gathered directly from the design where as in XPE you have to enter all the information. When running Report Power , you can export all the physical and functional information to an XPE exchange (. xpe ) fifi le which can be easily imported into XPE tool. While XPE has very high-level design information and less model accuracy compared to Vivado, exporting design information from Report Power to XPE can be very helpful for multiple use cases.

One use case for this flfl ow is to do a what-if analysis at post synthesis design stage. When the power reported in Report Power exceeds allocated budget, the design can be exported to XPE to evaluate power saving ideas without actually making any RTL changes. For example, you can evaluate how much power reduction can be achieved by reducing the resource usage or changing confifi gurations of blocks like BRAMs and DSPs. The impact of using different parts or environment settings and different voltage options can also be studied very easily. Snapshot and graph features of XPE come in very handy while doing several what-if analysis.

Another use case is to do a more accurate early estimation for the next generation of the design, which may reuse some design components from the current design. For example, if the next-generation design is going to use most of the similar design elements, then you can import the current .xpe fifi le to XPE and make changes to sheets where the design change is predicted. Often the next generation of Xilinx FPGAs are supported in XPE relatively earlier than Vivado. In such cases, export– import flfl ow is very helpful to study power profifi les on not only existing devices but also future devices.

TABLE OF CONTENTS

Operating Conditions

Power Constraints

Activity Propagation

Export– Import Flow with XPE