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XPE is a predesign phase tool meant to be used early in the project cycle to come up with power budgets for FPGA. It also helps Xilinx to provide customers an opportunity to explore power profifi les for future devices. In the backend, XPE implements power models which take in user-entered information and generate a power number. The power models go through multiple stages— Preview for models based on early device design specififi cation, Advanced for models based on device design simulation, Preliminary for models based on measurements on early silicon, and Production for models based on production silicon measurements.
XPE being Microsoft Excel-based tool, it retains a majority of Excel capabilities. It is divided into several sheets; several of them are dedicated to a specififi c resource type on the FPGA. On Summary sheet, device selection and environment setup can be explored. It also contains detailed power report. Snapshot sheet allows to compare power reports between different settings. There is also a blank user sheet which retains all the Excel functionality. It can be used in a variety of ways, from scratch space to detailed system level block diagram, and can cross-reference data from rest of the sheets.
Apart from exploring different device and thermal setup for optimal static power, it is also important to explore the relative dynamic power impacts across different confifi gurations of various blocks. For example, Transceiver sheet mainly asks for basic transceiver-related inputs like channel count , data rate , data width , and operation modes . Besides these, you can do a what-if analysis to see power savings of choosing low-power mode ( LPM ) over decision–feedback equalization ( DFE ). This sheet can also estimate the additional power of using eye scanning, out of band (OOB) sequence generation, or any hard IP blocks with a given transceiver.
One more example is the I/O sheet which asks for basic I/O characteristics like data rates , toggle rates , enable rates , and pin confifi gurations . It also gives the capability to do a what-if analysis between high-performance ( HP ) and high-range ( HR ) I/O banks. It gives an extensive and intelligent drop-down list of IO standards depending on availability in selected I/O bank and device. For more accurate estimation, advanced users can also provide input termination and output impedance when they are supported by selected I/O standard.
Manually entering entire design data in XPE can be tedious and confusing at times. To aid in this, XPE provides various wizards— Quick Estimate , Memory Interface Confifi guration , Memory Generator , and Transceiver Wizard . Quick Estimate wizard is to do a very quick and coarse power estimation. The remaining wizards are for ease of design data entry. For example, you can use Transceiver Wizard to choose from a variety of protocols from the drop-down menu and enter few key information like data rate , clock , etc., and it will not only populate the Transceiver sheet but also add link layer logic information in the Logic sheet. XPE also allows you to delete the design data added through one of the above wizards by using Manage IP wizard.
As a fifi nal note, XPE can only be as accurate as the data entered. Often, it is very diffifi cult to estimate power accurately because accurate switching activity and design information is not known very early in the design cycle. If suffifi cient information is provided, XPE can estimate device static , I/O , and Transceiver power with reasonable accuracy. However, it still does not have suffifi cient design connectivity information to accurately estimate core dynamic power. Since power budgets are frozen early in the design cycle, it is important to account for this uncertainty early on.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
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Manufacturer:Xilinx
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Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
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