Simulation of Behavioral/RTL Model

Simulation of Behavioral/RTL Model

Initially (before synthesis) only RTL design is available, and simulation can be performed on it via selecting run simulation from Flow Navigator window and further selecting run behavioral simulation . This is the fastest simulation and any issue found at this stage is the easiest to fifi x. After synthesis and implementation, the run simulation will also let you run post-synthesis functional/timing simulation and post-implementation functional/timing simulations, respectively. These simulations are more accurate but considerably slower.

Simulation Steps

On running simulation, Vivado internally calls launch_simulation command to run the simulation and displays the initial result. launch_simulation is the command for not just Vivado simulator but also for other integrated simulators. To select the appropriate simulator, set the property TARGET_SIMULATOR to one of XSIM , ModelSim , IES , or VCS . The default value is XSIM.

set_property TARGET_SIMULATOR <name>

launch_simulation script does the following:

• Determines design sources, including fi les

• Determines the order of parsing (if requested)

• Compiles all Verilog and System Verilog fi les with xvlog

• Compiles all the VHDL fi les with xvhdl

• Elaborates the design into simulation snapshot using xelab command

• Opens up design scope window, objects window, and waveform window to monitor the simulation

• Runs simulation on the snapshot using xsim command for a pre-specifi ed simulation time

• Gives control back to Tcl shell for further simulation commands or for inspection of design or output

Some of the options for launch_simulation that might be of interest to you are:

• step : Fine control of simulation stage to perform. Values are compile , elaborate ,

simulate , and all (default is all ).

• scripts_only : Only generate the simulation scripts; don’t actually execute the scripts.

• noclean_dir : After simulation run, don’t clean up the directory.

Any error in compilation or elaboration of the HDL fifi les will be reported in the messages as well as log tab at the bottom of Vivado. The error messages in the message tab has hyperlink to the source for speeding development. Output of simulation can be observed in log window of Vivado.

Objects window.png

Scope can be browsed on the scope window . On selecting a scope, all the signals in the scope are displayed in the objects window as in Fig. 11.1 . Once the scope is changed, the object window will start displaying signals of the new scope. This objects window displays the current value of the signal. Vivado picks the default radix to display the value. This radix can be customized by the pop-up menu on right click over the signal. To see previous values at specififi c time, waveform viewer can be used. This is explained in Sect. 11.3.6

Some of the Tcl commands related to scope are:

• current_scope without any argument: Returns the name of the current scope.

• current_scope <name> : The scope is changed to the specifi ed name.

• get_scopes: Lists all the child scopes of the current scope.

• report_scopes Describes all the child scopes of the current scope.

The following is an example transcript:

current_scope /counter_tb

/counter_tb

get_scopes

/counter_tb/dut /counter_tb/Initial28_0 /counter_tb/Always35_1 /

counter_tb/Monitor32_6

report_scopes

Verilog Instance: {dut}

Verilog Process: {Initial28_0}

Verilog Process: {Always35_1}

Verilog Process: {Monitor32_

Timing Simulation

Xilinx maintains libraries with and without timing information. Library without timing can be used for faster verififi cation of functionality. However, if you want to also consider the individual gate and wire delays, you should use post-synthesis timing simulation . In this mode, the simulators will also flfl ag if any of the timing checks as they are violated during simulation. Post-implementation timing simulation uses. SDF fifi les generated from Vivado to model more accurate wire delays and timing checks.

Controlling Simulation from Tcl

Simulation in Vivado will run for time duration specififi ed in simulation options and will stop for further commands. Simulation can be continued with the Vivado command run . run runs the simulation further from the currently stopped time.

run 100 #runs simulation for 100 ns (ns is default time unit for simulation)

run 100 us #runs simulation for 100 micro second (timeunits are ms, us, ns, fs)

run –all #runs simulation till there are no more process in the design

Current simulation time can be observed with the command Vivado Tcl command current_time . To redo the simulation without the overhead of re-compilation, there is the Vivado Tcl command reset_simulation . This resets the simulation time to 0 and cleans up any fifi les or data generated during simulation. If you are debugging and want to preserve breakpoints and conditions , you will need to use the command restart instead of reset_simulation .

Waveform Window

During simulation, Vivado generates a waveform database and displays it in the waveform window. When simulation is done for the fifi rst time, Vivado automatically displays all the signals at the top level of the design. You can add signals to waveform window by dragging signals from the objects window to the waveform window. Or, you can use the Vivado Tcl command add_wave with hierarchical or relative signal name. You can customize the waveform being added through the use of the following switches to add_wave:

• radix : To set the radix for displaying the values. Valid radix types are bin, oct,

hex, dec, unsigned or ascii.

• after_wave/before_wave : To customize the placement of the wave. By default,

the new waveform is added at the bottom of the existing waveforms.

• color : To set the color of the waveform, which can be a standard color name or a

string of the form ##RRGGBB.

• r : Used to add all signals under the specifi ed scope.

If you have customized your waveform, you can save the customization as waveform confifi guration, to be loaded during future simulation of the same design. To save a waveform confifi guration, select the waveform and press Ctrl-S . The confifi guration gets saved as a *.wcfg fifi le . It is possible to save multiple waveform confifi gurations into separate wcfg fifi les. For restoring a stored waveform confifi guration, select fifi le→open waveform confifi guration from the menu and select the *.wcfg fifi le.

Waveform viewer also has an ability to display the data in analog form, as shown in Fig. 11.2 . It can be very useful in visualizing signal processing data. To see analog wave , right-click on the signal and select waveform style as analog.

Analog waveform.png

Source window with breakpoints.png

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