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For simulating the design, you need to specify a testbench . The testbench contains HDL fifi le(s) which provides the input to the design for simulation. It also prints and/ or checks the outputs. A more complex testbench may even do white box testing by performing assertion checks on internal signals of the design.
You need to add these testbench fifi les in addition to the design fifi les. While adding source fifi les from the GUI menu ( fifi le → add sources ), Vivado provides an option to add or create simulation source . You need to select this option for testbench fifi les that are not part of the design being implemented on the FPGA. These testbench fifi les are used (along with the design fifi les) for the purpose of simulation. Vivado determines the HDL language and variants through the fifi le extensions. For example, fifi les with .sv extension are considered as of type SystemVerilog .
Each simulator provides some options that you need to set appropriately. You can select the simulator and set the options by clicking on simulation settings. Simulation is done in three stages Compilation, Elaboration and actual Simulation. Each stage has its own set of options.
Compilation is the stage where Verilog, VHDL, or System Verilog is read and a parse tree representing the model is created and stored in the design library. Most of the language-related errors are detected at this stage. XSIM compilation for Verilog/ SystemVerilog and VHDL is performed by xvlog and xvhdl , respectively. Some of the options for xvlog/xvhdl are:
• Verilog options: To add and include paths for searching ‘include d fi les and also for defi ning Verilog macros ’defi ne from command line
• Generics or parameter options: To change the default parameters for top-level module or entity
• nosort : To prevent Vivado from trying to auto-determine the dependencies across HDL fi les to determine the order of parsing
• relax : To show some leniency toward LRM noncompliance but commonly used styles in HDL Elaboration Elaboration is the stage where parse trees are combined based on design hierarchy; parameters are resolved and a simulation kernel code corresponding to the HDL code is generated inside a design snapshot. XSIM elaboration is performed by xelab command. Some of the options for xelab are:
• snapshot : To specify the name of design snapshot meant for simulation. Default name is top-level module/entity .
• debug_level : To specify the level of debug that may be performed. It impacts the level of optimization that can be performed by the simulation engine. Values could be:
– typical : For line tracing, waveform display, and deriver debugging
– all : All of typical and debug of Xilinx precompiled library
– off : No debugging. Provides the fastest simulation
• relax : To show some leniency toward LRM noncompliance but commonly used styles in HDL.
• mt_level : To use multi-threading for faster elaboration.
– auto : Determined the level automatically, based on machine confi guration.
– off : No multi-threading
– <num>: use max of <num> threads
Simulation is the fifi nal stage where the simulation kernel corresponding to the design is verififi ed and debugged by running it. In the context of Vivado’s inbuilt simulator, xsim is the command for the actual simulation using the generated design snapshot. Some of the options for simulation are:
• runtime : Time for which simulation should be run, before stopping. In a typical simulation, it is the setup time, after which initial simulation stops and control is returned to Tcl shell. Simulation can continue further from Tcl shell with commands run –all or run <time> .
• wdb : The waveform database fi le that is generated from simulation. This database can be viewed by Vivado waveform viewer.
• saif/saif_all_signals : Used to generate SAIF fi le for power analysis.There are also additional options under compilation/elaboration and simulation tabs which can be used for passing any options to the parser ( xvlog/xvhdl ), elaborator ( xelab ), or simulation engine ( xsim ).
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