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The output from HLS is used as RTL input to the remainder of the FPGA design fl ow. The HLS output is provided in industry standard RTL format (Verilog and VHDL) and in gate-level format ( EDIF ). The most productive methodology for using the outputs of HLS is the one which uses an IP integration fl ow where the RTL output from HLS is another IP block in the RTL system along with existing RTL IP.
An IP integration environment allows the IP blocks, including the HLS-generated RTL design, to be easily integrated into the chip-level design, and is explained in Chap. 7 . It would typically take more effort to add the HLS IP into the chip-level RTL design manually (connecting each port in a text editor), than using IPI. Since IPI uses IPs based on AXI protocol, you are highly encouraged to use AXI interfaces for your HLS designs, allowing the HLS IP to easily be integrated into your FPGA RTL design using the IP integration environment.
The fi nal part of any productive C-based design fl ow is the use of a Tcl script to take advantage of batch processing. Batch processing through Tcl is supported by HLS, allowing C simulation, C synthesis, RTL verifi cation, and RTL IP integration to be performed effi ciently in batch mode.
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