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Automatic RTL verifi cation is a feature of HLS. Since the HLS tool knows the inter- faces which are created in the RTL, it is possible to automatically create an RTL testbench to verify the RTL output from HLS. This allows the RTL to be verifi ed without the requirement to create an RTL testbench.
Since the RTL verifi cation is based on the C testbench, the amount of verifi cation which is performed on the RTL is exactly correlated with the effort spent writing a C testbench which exhaustively verifi es all modes. As stated earlier, spending time and effort to create a C testbench which exhaustively tests all modes is a productive investment, since C simulation is fast and productive and the investment in this is automatically leveraged into the RTL verifi cation.
RTL verifi cation typically takes substantially longer to complete than any other part of a C-based design flow. It is therefore recommended to only perform RTL verifi cation when the design exploration process is complete or whenever you wish to take a representative sample through the remainder of the design flow.
Verification confi rms the behavior of the RTL matches the behavior of the C code simulation. To verify the RTL in the context of the other RTL blocks in the full FPGA design, the RTL output must be integrated into the FPGA RTL design project.
Manufacturer:Xilinx
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Manufacturer:Xilinx
Product Categories: Socle de fusible
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Manufacturer:Xilinx
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Manufacturer:Xilinx
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