A Productivity Data Point

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For the minmax_frame example used throughput this chapter:

• Writing the C code, the C testbench, and performing C simulation to verify the results took approximately 45 min.

• The run time to generate each of the three HLS solutions shown in Fig. 10.10 is approximately 3 min per solution.

• Between each solution, the time to determine, select, and apply the optimization directives is approximately 5 min.

• Within approximately 1 h, these solutions represent three unique RTL imple- mentations and 1500 lines of RTL HDL code.

Since the clock frequency and target technology are input parameters to HLS, this design may be targeted to a new target technology or a new clock frequency and new RTL generated in a matter of minutes. Although this is a small demonstrative example, the productivity benefi ts scale when working on larger designs.

XCV200E-6CS144I

Manufacturer:Xilinx
FPGA Virtex-E Family 63.504K Gates 5292 Cells 357MHz 0.18um Technology 1.8V 144-Pin CSBGA
Product Categories: Batterie

Lifecycle:Obsolete -

RoHS: No RoHS

XCV200E-6FGG456C

Manufacturer:Xilinx
FPGA Virtex-E Family 63.504K Gates 5292 Cells 357MHz 0.18um Technology 1.8V 456-Pin FBGA
Product Categories:

Lifecycle:Obsolete -

RoHS:

XC4028XL-3HQ304C

Manufacturer:Xilinx
FPGA XC4000X Family 28K Gates 2432 Cells 0.35um Technology 3.3V 304-Pin HSPQFP EP
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Obsolete -

RoHS: No RoHS

XCV200E-7FG456C

Manufacturer:Xilinx
FPGA Virtex-E Family 63.504K Gates 5292 Cells 400MHz 0.18um Technology 1.8V 456-Pin FBGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Obsolete -

RoHS:

XCS30-3PQG208I

Manufacturer:Xilinx
Xilinx QFP-208 Voltage regulator tube
Product Categories: Voltage regulator tube

Lifecycle:Obsolete -

RoHS: -

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