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Any methodology for creating an optimal RTL implementation ideally requires understanding what the requirements of the RTL implementation are. However, the following methodology assumes you wish to create the highest-performing design. If this is not the case, skip steps 4 and 5:
1. Simulate the C design and ensure the results are checked in the testbench.
2. Synthesize the C code to create a baseline design. This will be the default syn- thesis performed by HLS and provide you with a starting point for optimization.
3. Apply the optimizations for interface synthesis. This ensures the interfaces are of the required type to integrate the design with the rest of the system.
4. Apply pipeline directives.
5. Address any structural issues which create bottlenecks and prevent pipelining achieving the desired II , such as partitioning arrays and unrolling loops.
6. Use the optimization directives which control the allocation of resources to improve the area if this is required.
7. Finally, if the latency is a performance requirement, specify any latency directives.
Fig. 10.10 Example design implementations
This methodology can be applied to the minmax_frame function to create three data points for design comparison. The clock frequency is specifi ed as 4 ns and a Kintex7 device is targeted.
The performance and resources for the three examples are shown in Fig. 10.10 . Remember that this design example has eight input values and therefore the reported II is the number of cycles before another eight new inputs can be processed.
Example 1: Small Design
• Input array DataIn is specifi ed as a block RAM interface.
• Both outputs are specifi ed with an output valid signal.
• A block-level IO protocol is specifi ed.
• The loop is left rolled.
Leaving the loop rolled ensures the minimum amount of hardware; however, the latency and II are the highest because HLS creates logic to implement the body of Loop1 and then executes the same logic eight times sequentially (calculating each iteration of the loop before starting to calculate the next iteration).
Example 2: Fastest Design
• Input array DataIn is completely partitioned into eight separate ports.
• Since the input array DataIn is read in sequential order, it is specifi ed as an AXI- Stream to reduce resources (no address generation logic) resulting in eight sepa- rate AXI-Stream interfaces.
• Both outputs are specifi ed as AXI-Stream interfaces.
• A block-level IO protocol is specifi ed.
• The loop is fully unrolled.
Unrolling the loop creates a design with the largest amount of hardware—eight copies of the logic required to implement the loop body—and partitioning the input ports allows parallel reads and writes. This creates the fastest design but also uses the greatest number of resource. If the clock frequency is reduced, this design can complete in a single clock cycle.
Example 3: Pipelined Design
• Since the input array DataIn is read in sequential order, it is specifi ed as an AXI- Stream to reduce resources.
• Both outputs are also specifi ed as AXI-Stream interfaces.
• A block-level IO protocol is specifi ed as an AXI-Lite interface.
• Loop1 is pipelined.
Pipelining the loop keeps the hardware to a minimum while still ensuring the design is able to process one sample per clock cycle ( II = 8: the design can process eight inputs in eight clock cycles).
The ability to generate multiple RTL implementations from the same C code is a large productivity benefi t of using HLS. You are able to explore the design space to create the most optimum design implementation.
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