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Performance in HLS is measured by the design latency and initiation interval ( II ). Figure 10.7 shows an example design which takes fi ve clock cycles to complete. It starts in state S1 where it performs a read on the data port and proceeds through to state S5 where the output is written.
• The latency is defi ned as the number of cycles it takes to complete all outputs. In Fig. 10.7 , the latency is fi ve clock cycles.
• The initiation interval ( II ) is defi ned as the number of cycles before the design can start to process a new set of inputs. In Fig. 10.7 , the next read is not performed until the design has completed, and hence the II is six clock cycles.
Both latency and II may be specifi ed using optimization directives. Typically, the key performance metric is the II : how quickly the design processes new input data and produces output data. In most applications, the goal is to create a design which can read new inputs every clock cycle ( II = 1).
Fig. 10.7 HLS performance metrics
The resources used to implement the design may also be considered a performance metric. HLS provides reports which specify how many LUTs, flip-flops, DSP48, and block RAMs are used. Optimization directives may be used to control the number of these resources; however, doing so impacts the latency and/or the II .
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Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
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Product Categories: FPGAs (Field Programmable Gate Array)
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