Controlling the SYSMON Operation

The SYSMON has a rich set of registers which can be accessed in three different mechanisms of interfaces (Fabric DRP access, I2C access, JTAG TAP access). Figure 16.5 shows the SYSMON register set. The access for up to 256 registers is allowed which are of 16-bit wide each, by any of the three interface mechanisms mentioned above. You need to follow the timing relation of different DRP ports while accessing these registers through fabric interface. The fabric register access is referred with respect to the DCLK.

SYSMONE1 register interface.png

SYSMON Control Registers

The Control Registers are used to configure the SYSMON operation. All the SYSMON functionality is controlled through these registers. These Control Registers are initialized using the SYSMON attributes when the SYSMON is instantiated in a design. This means that the SYSMON can be configured to start in a predefined mode after the FPGA configuration.

The Control Registers are further classified into:

• Configuration Registers (address range 0x40h to 0x43h)

• Sequence Registers (address range 0x46h to 0x4Fh and 0x78h to 0x79h)

• Alarm Registers (address range 0x50h to 0x6Fh)

The Configuration Register has bits associated with operating modes like Sequence Mode, Single-Channel or External Multiplexer Mode (Auto Channel Sequencer), Continuous or Event Trigger Mode, Averaging Mode on selected channel, Channel Sequencing operation, Calibration settings, etc.

Along with the Control Register configuration, there are multiple Sequence Registers available that need to be configured in order to help SYSMON to operate in the correct manner. In case of Single-Channel mode, the Control Register needs to be set to select only one of the available channels. In cases, when multiple channels need to be monitored, then Auto Channel Sequencer Mode is enabled. Based upon predefined sequence of channels defined in the Channel Sequence Register (SEQCHSEL), the sequencer automatically selects the next channel for conversion, sets the averaging (SEQAVG), configures the analog input channels (SEQINMODE), sets the required settling time for acquisition (SEQACQ), and stores the results in the Status Registers.

The ADC Channel Averaging Registers (SEQAVG) enable and disable the averaging of the channel data in a sequence. The result of a measurement on an averaged channel is generated by using 16 or 64 or 256 samples, which is controlled through Configuration Register bits. Offset correction enablement is also configurable option for ADC and supply sensors.

The SYSMON provides mechanism to raise the user intervention for any adverse condition occurring in the system using Alarm Registers. The Alarm Registers are used to set up the automatic alarms once the channel input signals crossover the limits set by you. The alarms are generated on 16-bit ALM port. You can program the alarm thresholds in the Control Register address range of 0x50h to 0x6Bh. The alarm for particular input will be set up both for the lower as well as higher limits. The alarms are reset when a subsequently measured value falls inside the threshold (min and max) ranges.

The on-chip temperature measurement is used for critical temperature warnings and also supports automatic shutdown of the FPGA device to help prevent the device from being permanently damaged. During very high temperature scenarios beyond 125 °C, the FPGA device is auto shut down; however this option needs to be enabled separately by you through configuration of the Over Temperature (OT)upper Alarm Register. The device auto-shutdown facility is disabled by default. During FPGA shutdown the SYSMON still maintains its data using the internal clock oscillator. The auto-shutdown facility is really useful as it prevents the device from getting permanently damaged. Once the on-chip temperature reduces, it is necessary to reconfigure the device for further usage.

User application can keep watch on the temperature alarm signals and should take the necessary action like turning on the cooling system, etc.

SYSMON Status Registers

The SYSMON Status Registers are read-only registers, which have the updates of all the measurements carried out by the SYSMON ADC. These registers can be accessed at the address range of 0x00h to 0x3Fh and 0x80h to 0xBFh. For each of the ADC capabilities, one individual register is provided. It includes parameters like on-chip temperature, different on-chip voltages (VCCINT, VCCAUX), external analog channel registers, etc.

There are two more set of Status Registers which are categorized in MAX and MIN type, which store the maximum and minimum values of these parameters since the FPGA is powered on or since last reset of SYSMON. The MAX and MIN set of registers are different than the regular set of registers which stores the latest ADC conversion values. The Flag Registers (address range 0x3Eh, 0x3Fh) are considered to be part of Status Registers with each bit indicating the status of parameters for various alarms and Over Temperature (OT).

SYSMON can be digitally calibrated to phase out any offset as well as the gain errors in ADC and power supply sensors using the Calibration Registers which are also part of the Status Registers (address range 0x08h to 0x0Ah). A built-in calibration function automatically calculates these coefficients.

TABLE OF CONTENTS

SYSMON Control Registers

SYSMON Status Registers