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Using the SYSMON in System Design

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As per the requirements for the system design, you can directly instantiate the hard  macro template in the design RTL files and use appropriate interface ports as per the  required configuration. The RTL instantiation template is available in Vivado under  Advanced Device Primitives. Xilinx also provides the SYSMON Wizard IP core under  Vivado IP catalogue, which helps the user to pre-configure the SYSMON for FPGAbased system applications. Figure 16.2 represents the UltraScale-based SYSMON  primitive level diagram showing ports of different groups and interfaces.

It is expected that you should be familiar with each of the SYSMON ports group  and its intended usage in their application when SYSMON is incorporated in the  design. The Dynamic Reconfigurable Port group is mainly used to access the internal  set of registers. Control and Reset port group is used to control the reset as well as  controlled conversion start access. The External Analog Input ports are the main  ports for you to connect up to 16 external analog channels to be monitored, while  the VP/VN are dedicated input ports. The 16 analog inputs are actually FPGA  general-purpose IOs, while the VP/VN pins are non-shared pins. If VP/VN is not  used, then these pins cannot be used for any other general-purpose IO usage and 

Simplified block diagram of UltraScale FPGA-based system monitor.png


Evolution of SYSMON in Xilinx family of FPGA devices.png

need to be connected to analog ground. SYSMON also provides indicators for any  adverse conditions through ALARMS group of signal. Your application can connect  this group of signals to the monitoring LEDs on the board. The Status Group of  signals mainly indicates the end of current conversion cycle, which channel is at  present under process, status of JTAG access of registers suit, etc. The I2C DRP group of signals is used to provide two-wire standard low-cost I2C protocol access  by external I2C master. These are the main peripheral ports you need to be aware  while planning the system-level designs along with SYSMON.

SYSMONE1 primitive port structure in the UltraScale FPGA devices.png

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