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C synthesis may be thought of as two separate processes: interface synthesis and design synthesis (although both are very much intertwined). Interface synthesis is the process of converting the arguments of the design function from simple data values to an RTL cycle accurate interface which optionally may include an IO protocol.
The minmax_frame example shown in Fig. 10.3 helps demonstrate the concept of interface synthesis. Figure 10.5 shows the top-level function for synthesis with arguments DataIn , min , and max . After synthesis, these C arguments may be trans- formed into RTL interfaces shown (in both Verilog and VHDL) in Fig. 10.5 .
A clock and reset are added to the RTL design. The tool provides options to con- trol whether the reset port is active-high, active-low, or if it is present at all.
Each of the data arguments from the C function— DataIn , min , and max —are trans- formed into RTL data ports with associated interface protocol signals. In this particu- lar case, the array DataIn is transformed into a block RAM interface. This interface protocol assumes array DataIn is a block RAM outside the design and is therefore accessed with standard block RAM address, data, and chip-enable signals. In this case, HLS determined this port is only ever read and hence there is no requirement for a write-enable ( WE ) port.
Similarly, HLS automatically determined arguments min and max are only written to and hence these are implemented as output ports in the RTL design. In the example shown in Fig. 10.5 , both ports are implemented with an associated output valid signal to indicate when the data is valid.
Fig. 10.5 Interface synthesis
Interface synthesis provides many options for interfaces. The array DataIn could also be implemented as an AXI master or AXI-Lite interface. If the array is accessed in a streaming manner, with each address location accessed in sequential order (as in this case), the DataIn port may be implemented as an AXI-Stream interface, or a FIFO interface, or a two-way handshake interface.
In a C-based design fl ow, it is highly advisable to synthesize the interfaces with IO protocols. This allows the fi nal RTL design to be simply connected to other RTL blocks during the RTL integration phase without you manually trying to determine when the data may be read or written.
In addition to the port-level IO protocols, HLS may optionally add a block-level IO protocol as shown in Fig. 10.5 . A block-level IO protocol is a protocol which is associated with the design or block, rather than any particular port. In Fig. 10.5 , the ap_start port controls when the block can start its operation, the ap_ready indicates when the design is ready to accept new input data, and the ap_done and ap_idle signals indicate when the design has completed its operation and is idle. Block-level IO signals may also be implemented as an AXI -Lite interface allowing the RTL IP to be easily controlled from a CPU or microcontroller.
The block-level IO and port-level IO protocols also help enable automatic veri- fi cation of the RTL. Given a handshake protocol on both the design and the IO ports, it is always possible to automatically generate an RTL testbench. Without these handshake protocols, it may only be possible to automatically generate a testbench for certain cases. Even if the IO protocols are not required for the design, it is worth considering that the small overhead in logic means you do not have to write an RTL testbench.
As with synthesis in general, the HLS tool will have a default interface protocols for each type of C argument (arrays, input pointers, output pointers, etc.). You can then use directives to specify interface protocols other than the defaults.
As noted earlier, HLS provides many options for selecting interface protocols. Figure 10.6 shows some examples of the type of interface which may be created for the minmax_frame C code example shown in Fig. 10.3 :
A. This is the case shown in Fig. 10.5 . The array is implemented as a block RAM interface, and the output ports are implemented with output valid signals.
B. In this case, the array is partitioned into discrete elements and each is imple- mented as an AXI-Steam interface. Since N is 8 in the minmax_frame example,
Fig. 10.6 
there are eight discrete ports for the inputs, allowing all inputs to be read simultaneously.
C. In the fi nal case, since all data accesses are sequential in this example, both the input array and the output ports are implemented as AXI-Stream interfaces. Also, in this example the block-level IO protocol is implemented as an AXI-Lite interface.
Once you have selected the IO protocols, HLS design synthesis then optimizes the internal logic to maximize the performance of the design.
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