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An overview of the HLS process is shown in Fig. 10.4 . A key difference between RTL design and C-based design is that HLS synthesizes a single top-level C func- tion into an RTL design which is then incorporated as an IP block into a larger RTL design. The C function is never the top level of an FPGA design; rather HLS is used to quickly create RTL IP blocks which are then assembled in an RTL environment.
The inputs to HLS are the C design function, a C testbench to verify the behavior of the C design function, and design constraints and optimization directives to specify the performance and structure of the RTL design.
The design constraints are the target technology and the clock frequency. The target technology specifi es the component delays. Given the component delays and the clock frequency, HLS creates an RTL design which meets timing after RTL synthesis. HLS determines how much logic can be executed in each clock cycle and then creates an FSM to sequence the design operation. It can be expected that when targeting a newer and faster technology, HLS is able to perform more operations within a clock cycle, and hence fi nish in fewer clock cycles, than when targeting an older and typically slower technology.
Optimization directives may be used to specify the performance and area of the RTL design. During the synthesis process, the HLS tool will perform some default optimizations. These defaults are specifi ed in the documentation provided with the HLS tool. Optimization directives are used to create an RTL design with optimiza- tions which are different from the default synthesis, e.g., to vary the area- performance trade-off point.
The outputs from HLS are an RTL design and reports which detail the perfor- mance of the design and an estimate of the maximum delays and the resources required to implement the design. At this point in the design process, only estimates of the timing and area are reported—the exact details cannot be known until RTL synthesis and Place & Route are performed—however, the estimates are generally accurate (±10 %).
Fig. 10.4 High-level synthesis design flow
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