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C simulation is the process of compiling and executing the C program and is the most underappreciated part of a C-based design fl ow. The benefi ts of C simulation can be summarized as speed, speed, and speed. It is while performing C simulation that you actually design—create an algorithm, simulate the algorithm, review the results, refi ne the algorithm, simulate the algorithm, review the results, etc. The fast compilation and execution times of C simulation allow these design iterations to be performed quickly and productively.
Fig. 10.2 Testbench and design function
As highlighted in Fig. 10.2 , the top level of every C program is the main() function. In a C-based hardware design fl ow, the C program is considered to be two separate components, the C testbench and the design function to be synthesized into hardware.
In the example in Fig. 10.2 , the C program contains eight sub-functions, f1–f8 . Function f3 is the top-level function for synthesis, and everything below function (including) f3 is the design function to be synthesized (functions f3 , f7 , and f8 ). The C testbench is everything below (including) the level main() excluding the design functions (functions main() , f1 , f2 , f4 , f5 , and f6 ). The testbench creates input for the design function and accepts output from the design function and hence is used to verify the design function.
A key part of any productive C-based design fl ow is an intelligent testbench: one which both analyzes and verifi es the results from the design function. Figure 10.3 shows an example C design and testbench. The design function, shown on the left- hand side, is a simple design which reads a set of input data from array DataIn and determines the minimum and maximum values in the data set. The C testbench, shown on the right-hand side, creates a set of input data, calls the design function, analyzes the output results from the design function (in this simple example, by comparing them to the expected results), and sets the return value to main() as zero only if the results are correct.
In a more complex design than the example shown in Fig. 10.3 , the input data may be read from a data file on the disk, and the output results may be compared against golden results also read from a data fi le or from results generated in the testbench. The concept however is the same. C simulation is used to exhaustively verify the design and the C testbench is used to exhaustively analyze the results.
A final important point on the topic of the testbench is its re-use later in the design flow. HLS provides an automated RTL verifi cation feature: the HLS tool will generate an RTL testbench to verify the RTL output. If the C testbench checks the results, an RTL testbench can be created which automatically checks the results after RTL simulation .
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