Guidelines to Get Best Results Out of Synthesis

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• Understand your target architecture, so that you can fully exploit all its capabilities.

• Avoid using too many attributes that could hinder synthesis optimizations. Few of them are like DONT_TOUCH /MARK_ DEBUG . Debug comes with the cost of additional area/timing penalty. So make sure you understand the intent.

• Look at log fi le for synthesis info/warning messages, mainly on attributes and if any pipeline registers for block RAM/DSPs are missing.

• There is a misconception that heavy pipelining would make the design meet tim- ing easily. This might have an adverse impact. The reason is too many registers would make packing diffi cult. Maintain a good ratio of LUT to register, in the range of 1.5. If the ratio is less, relook if pipelining is more than needed.

• Look at logic level distribution post-synthesis. If there are too many paths at the higher side, use a systematic approach to distribute these. Few of the tricks learnt in this chapter should come handy.

XC4003-6PG120C

Manufacturer:Xilinx
FPGA XC4000 Family 3K Gates 100 Cells 100MHz CMOS Technology 5V 120-Pin CPGA
Product Categories:

Lifecycle:Obsolete -

RoHS: No RoHS

XC3064A-6PQ160C

Manufacturer:Xilinx
FPGA XC3000 Family 4.5K Gates 224 Cells 135MHz 5V 160-Pin PQFP
Product Categories:

Lifecycle:Obsolete -

RoHS: No RoHS

XC5VFX70T-2FF1136C

Manufacturer:Xilinx
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
Product Categories: Accessoire de fusible

Lifecycle:Active Active

RoHS: No RoHS

XC5VFX70T-2FFG1136C

Manufacturer:Xilinx
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Active Active

RoHS:

XC5VFX70T-3FF1136C

Manufacturer:Xilinx
FPGA Virtex-5 FXT Family 65nm Technology 1V 1136-Pin FCBGA
Product Categories: Connecteurs&adapteurs

Lifecycle:Unconfirmed -

RoHS: No RoHS

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Guidelines to Get Best Results Out of Synthesis